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參數(shù)資料
| 型號： | MT90503AG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | CLIP, STRAIN RELIEF, 50WAY; For use with:820 Series Tripolarized Wiremount Sockets; Ways, No. of:50; Material:Metal; Connector type:Strain Relief RoHS Compliant: Yes |
| 中文描述： | ATM SEGMENTATION AND REASSEMBLY DEVICE, PBGA503 |
| 封裝： | 40 X 40 MM, 2.33 MM HEIGHT, PLASTIC, MS-034, BGA-503 |
| 文件頁數(shù)： | 44/233頁 |
| 文件大?。?/td> | 1341K |
| 代理商： | MT90503AG |
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MT90503
Data Sheet
44
Zarlink Semiconductor Inc.
The control structure in Figure 10, TDM Channel Association: RX Channels (Non CAS mode) on page 44 indicates
the mode and options selected for the TDM channel. In the general TX structure, the RBW (RX Byte Write) bits
provide the format of the byte that is to be written over the RX byte in the circular buffer. While it is possible to write
over the low-byte, there are three possibilities provided if writing over the byte is chosen: writing a null byte or
generating one of two silence patterns. The detailed description of the dual-direction buffer is provided in the TDM
Circular Buffers section.
Figure 10 - TDM Channel Association: RX Channels (Non CAS mode)
In the receive direction, the control structure retains some of the recurrent features from the transmit structure. The
TX circular buffer/size field is the same, which is normal given that the TX and RX circular buffers are common. The
information on the address and size is encoded in the same way as in the TX structure.
For the reception structure, the high mode bit codes whether the RX channel is transmitting a channel received
from ATM or if it is retransmitting information taken from the TDM bus and written into a circular buffer. If the high
Mode bit is ‘0’, the channel is ATM; if it is ‘1’, the channel is TDM. By supporting a low latency TDM loopback, the
MT90503 conforms to the H.100/H.110 specification.
The C and U bits serve as status enable bits. These bits are R/W, and tell the register module whether the register
counters and status bits should report errors on this VC. The U bit is the underrun status enable: when this bit is set
and an underrun is detected, the TDM register module will increment the global underrun counter and set the
underrun detect status bit.
The C bit serves at the cut VC detect status enable. When this bit is at ‘0’, the UR count acts as a free running
256-underrun counter. In this case, it serves to compile the total number of underruns that have occurred. When the
C bit is at ‘1’, then the UR count serves as a detector for cut VCs. The counter resets to 0 each time a valid TDM
byte is received. If an underrun is received, the counter is incremented by one. If the counter ever increments from
254 to 255, then 255 consecutive
underruns have been received, indicating there is 32 ms of absent data. This is
interpreted as a cut VC and will generate an interrupt.
Cell-loss integration periods of greater than 32 ms can be supported by software. Upon UR Count reaching 255,
and subsequent interrupt to the CPU, the software can check that the count has not returned to zero (which
happens if the cells start to arrive again) at some interval equivalent to the cell-loss integration period.
b8
b9
b10
b11
b12
TX/RX Circular Buffer Address and Size
b13
b14
b15
+0
b0
OE
b1
b2
b3
b4
b5
b6
b7
+2
Reserved
Mode
TX/RX Circular Buffer Address and Size
: Address and size of the circular buffer in the data memory
from which data bytes will be
read
: Voice Stream Output Enable. This bit, when set, enables the driving of the Voice Data on the
stream.
Mode
: Channel Mode of operation.
“0000”=Normal PCM;
“1000”=Low Latency Loopback
others=Reserved.
C
: Cut VC Status Enable. When ‘0’, the
UR Count
field is freerunning(256 consecutive underruns will
bnot
UR Count
field is used as a consecutive underrun indicator
that stops incrementing at 255.
U
: Underrun Status Enable. When this bit is set and an underrun is detected, the status counters and bits
will report this event.
UR Count
: 8 bit underrun count. When the
C
bit is cleared, acts as a freerunning underrun error counter.
When the
C
bit is set, it is used as a cut VC detector. In this mode, the counter is cleared each time a
valid byte is received. It increments (to a maximum of FFh) each time a byte underrun is detected. When
a transition from FEh to FFh occurs, the Cut VC status register, counter and id fields are updated. Must be
initialized to FFh by software before enabling VC when
C
bit is set. Must be initialized to 00h by software
before enabling VC when
C
bit is cleared.
1
UR Count
U
C
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