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參數資料
| 型號： | MT90503AG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數字傳輸電路 |
| 英文描述： | CLIP, STRAIN RELIEF, 50WAY; For use with:820 Series Tripolarized Wiremount Sockets; Ways, No. of:50; Material:Metal; Connector type:Strain Relief RoHS Compliant: Yes |
| 中文描述： | ATM SEGMENTATION AND REASSEMBLY DEVICE, PBGA503 |
| 封裝： | 40 X 40 MM, 2.33 MM HEIGHT, PLASTIC, MS-034, BGA-503 |
| 文件頁數： | 58/233頁 |
| 文件大?。?/td> | 1341K |
| 代理商： | MT90503AG |
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MT90503
Data Sheet
58
Zarlink Semiconductor Inc.
4.3.2 TX_SAR Event Schedulers
4.3.2.1 Overview
The purpose of the transmit event scheduler is to ensure that the MT90503 assembles and transmits ATM cells at
the appropriate time. This timing function is implemented to reduce data overruns and underruns.
Before arriving at the TX_SAR, TDM channel data is written into a variable-length (128 to 1024 bytes) transmit
circular buffer, a construct in external data memory, by the TDM Module. Each TDM channel is assigned its own
transmit circular buffer (see section 4.2.6 TDM Circular Buffer Pointers). The transmit event schedulers determines
when the information will be assembled into ATM cells.
The 15 transmit event schedulers are identical, and all have individual configuration registers. Each transmit event
scheduler is divided into a programmable number of frames. When configured correctly, each transmit event
scheduler frame is constrained to an average of 125
μ
s (i.e. the time required for one byte to be
received/transmitted on each TDM channel).
4.3.2.2 The Transmit Event Scheduler Process
Please refer to Figure 24 - Transmit Event Scheduler Process in conjunction with this subsection.
The MT90503’s 15 transmit event schedulers are all maintained in a designated memory block in the external
control memory. Each transmit event scheduler can be programmed to support one of the four types of cells (AAL1
with or without pointer, CBR-AAL0, or AAL5-VTOA). Each of the transmit event schedulers can be enabled or
disabled via registers (0610h - 0616h) in order to use less bandwidth if a certain format of ATM cell is not required.
Figure 24 - Transmit Event Scheduler Process provides an example of one of the 15 transmit event schedulers in
the MT90503. All transmit event schedulers have exactly the same properties, and all perform the same functions.
They can be configured individually to handle different VC configurations.
Each of the 15 transmit event schedulers is made up of a number of “frames”, with each frame containing a number
of events. An event, if executed, consists of the assembling and placing in a UTOPIA output FIFO of one ATM cell.
The base address, length, and number of events can be programmed for each scheduler frame. Each transmit
event scheduler has its own Scheduler Base Address which, in conjunction with an internal frame counter, will
locate the events in a specific frame.
In order for an ATM cell to be assembled and transmitted at the appropriate time, the following transmit event
scheduler process steps are required:
An analogy can be made of the above process to a continuous “spinning wheel”, where there is a continual
selection and reading of events for each transmit event scheduler frame. Table 19 - Scheduler Event Fields
provides a description of the fields for one of the transmit event schedulers. Refer to Figure 24 - Transmit Event
Scheduler Process to locate the fields.
1
On the reception of a frame pulse, the scheduler scans through the events of the current frame.
2
For each valid event in the current frame, a cell is assembled and transmitted to the UTOPIA module.
3
On the reception of the next frame pulse (125
μ
s later) or upon the completion of the final valid event in
the current frame, whichever is later, the scheduler increments current frame, to point to the next frame in
the scheduler.
4
The scheduler reads each frame sequentially, returning to frame 0 upon completion of the final frame in
the scheduler.
相關PDF資料 |
PDF描述 |
|---|---|
| MT90520 | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MT90520 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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