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參數(shù)資料
| 型號(hào)： | MT90503AG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | CLIP, STRAIN RELIEF, 50WAY; For use with:820 Series Tripolarized Wiremount Sockets; Ways, No. of:50; Material:Metal; Connector type:Strain Relief RoHS Compliant: Yes |
| 中文描述： | ATM SEGMENTATION AND REASSEMBLY DEVICE, PBGA503 |
| 封裝： | 40 X 40 MM, 2.33 MM HEIGHT, PLASTIC, MS-034, BGA-503 |
| 文件頁數(shù)： | 46/233頁 |
| 文件大?。?/td> | 1341K |
| 代理商： | MT90503AG |
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MT90503
Data Sheet
46
Zarlink Semiconductor Inc.
23. Subsequently, each time that a byte is written to the circular buffer, the offset field is read, and an offset is
established between the internal TDM pointer and the pointer that will be used.
Figure 12 - TDM Channel Association: RX Channels (CAS mode)
The channel association structure for multiframe channels is slightly different, with only one bit being positioned
differently in the structure. While the circular buffer address and size field is still present and functions in the same
way, the mode bits are coded in the same way as they are in the transmit structure for multiframe channels. “0100”
is E1, “0110” is T1, and toggling the lowest bit of either of the numbers indicates that the FASTCAS method of
transmitting the data and CAS bytes are employed.
Four new fields are added to allow for CAS management on the RX side with multiframing:
Last RX CAS value that indicates the previous CAS bits received on ATM
The CAS monitor bit indicates if a change in the value of CAS is to be reported by the module
Man RX CAS is the value of CAS that can be inserted in the place of the one received. This value is only
used if the ME bit is set
ME bit Manual CAS insert
b8
b9
b10
b11
b12
TX/RX Circular Buffer Address and Size
b13
b14
b15
+0
b0
OE
b1
b2
b3
b4
b5
b6
b7
+2
Reserved
Mode
TX/RX Circular Buffer Address and Size
: Address and size of the circular buffer in the data memory
from which data bytes will be
read
: Voice Stream Output Enable. This bit, when set, enables the driving of the Voice Data on the even
stream.
Mode
: Channel Mode of operation.
“0100”=E1 Strict Multiframing;
“0101”=E1 FASTCAS;
“0110”=T1 Strict Multiframing;
“0111”=T1 FASTCAS;
others=Reserved.
C
: Cut VC Status Enable. When ‘0’, the
UR Count
field is freerunning(256 consecutive underruns will
be cosidered as a Cut VC). When ‘1’, the
UR Count
field is used as a consecutive underrun indicator
th t
U
: Underrun Status Enable. When this bit is set and an underrun is detected, the status counters and
bits will report this
event
: CAS Underrun Enable. When this bit is set and an CAS underrun is detected, the status counters
and bits will report this
UR Count
: 8 bit underrun count. When the
C
bit is cleared, acts as a freerunning underrun error counter.
When the
C
bit is set, it is used as a cut VC detector. In this mode, the counter is cleared each time a
valid byte is received. It increments (to a maximum of FFh) each time a byte underrun is detected. When
a transition from FEh to FFh occurs, the Cut VC status register, counter and id fields are updated. Must
be initialized to FFh by software before enabling VC when
C
bit is set. Must be initialized to 00h by
software
before enabling VC when
C
bit is cleared.
CM
: CAS Monitor. When ‘1’, any change in RX CAS value will be reported to the CPU. When an
underrun occurs, a CAS change will never be reported.
CO
: CAS Output Enable. This bit, when set, enables the driving of the CAS value out on the associated
odd TDM steam.
Last RX CAS
: This is the value of the last RX CAS sent on the TDM bus. This value is not written if an
underrun has occured for this CAS value,
ME
: Manual CAS Insert. When ‘1’, the
Man RX CAS
is sent instead of the CAS contained in the
l
memt
Man RX CAS
: CAS Value that is sent onto the TDM bus if
ME
= ‘1’.
1
UR Count
U
C
+4
+6
CU
CM
Last RX CAS
Man RX CAS ME
0
0
CO
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