參數(shù)資料
型號: M34559G6FP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP52
封裝: 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52
文件頁數(shù): 93/93頁
文件大?。?/td> 1810K
代理商: M34559G6FP
CLRC663
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Preliminary data sheet
COMPANY PUBLIC
Rev. 3.1 — 26 September 2011
171131
99 of 126
NXP Semiconductors
CLRC663
Contactless reader IC
The VCO frequency is divided by a factor which is defined by the output divider
(pll_set_divout). Of course only a limited accuracy of the output frequencies can be
achieved by this approach.Table 233 and Table 234: Shows the accuracy achieved for
various frequencies (integer multiples of 1 MHz and some typical RS232 frequencies) and
the divider ratios to be used. The register bit ClkOutEn enables the clock at CLKOUT pin.
The following formula can be used to calculate the output frequency:
fout = 13.56 MHz pll_set_divb /pll_set_divout
Remark: At the value 0 to 7 have special division values.
The following Table 235 shows the recommended divider values for typical clock
frequencies.
Remark: The recommended value for pll_set_divb = 00h (divider value = 23). In this case
the internal current consumption of the IntegerN PLL is a minimum.
Table 233: Setting of feedback divider pll_set_divb [1:0]
Bit 1
Bit 0
Division
00
23
01
27
10
28
11
23
Table 234: Setting for the output divider ration pll_set_divout [7:0]
Value
Division
08
19
210
311
412
513
614
715
88
99
10
...
253
254
Table 235. Divider values for selected frequencies using the integerN PLL
Frequency [MHz]
4
6
8
10
12
13
19
20
24
1.8432
3.6864
pll_set_divb
23
27
23
28
23
28
23
28
pll_set_divout
78
61
39
38
26
24
20
19
16
206
103
accuracy [%]
0.04
0.03
0.04
0.08
0.04
0.03
0.08
0.04
0.01
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