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參數(shù)資料
| 型號(hào)： | M34559G6FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52 |
| 文件頁數(shù)： | 87/93頁 |
| 文件大?。?/td> | 1810K |
| 代理商： | M34559G6FP |
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CLRC663
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Preliminary data sheet
COMPANY PUBLIC
Rev. 3.1 — 26 September 2011
171131
93 of 126
NXP Semiconductors
CLRC663
Contactless reader IC
13. FiFo Buffer
13.1 Overview
An 512
8-bit FiFo buffer is implemented in the CLRC663. It buffers the input and output
data stream between the host and the internal state machine of the CLRC663. Thus, it is
possible to handle data streams with lengths of up to 512 bytes without taking timing
constraints into account. The FiFo can also be limited to a size of 255 byte
13.2 Accessing the FiFo buffer
The FiFo-buffer input and output data bus is connected to the register FiFoData_Reg.
Writing to this register stores one byte in the FiFo-buffer and increments the internal
FiFo-buffer write-pointer. Reading from this register shows the FiFo-buffer contents stored
at the FiFo-buffer read-pointer and decrements the FiFo-buffer read-pointer. The distance
between the write- and read-pointer can be obtained by reading the register
FiFoLength_Reg. If the FiFo is used in 512 byte mode, also the higher bit of FiFoLength in
the FiFoControl_Reg register (bit 0 and bit 1) has to be taken into account.
When the
-Controller starts a command, the CLRC663 may, while the command is in
progress, access the FiFo-buffer according to that command. Physically only one
FiFo-buffer is implemented, which can be used in input and output direction. Therefore the
-Controller has to take care, not to access the FiFo buffer in an unintended way.
13.3 Controlling the FiFo buffer
Besides writing to and reading from the FiFo buffer, the FiFo-buffer pointers might be
reset by setting the bit FiFoFlash in FiFoControl_Reg to 1. Consequently, the FiFoLevel
bits are set to logic 0, the bit ErrIrq in the register Irq0_Reg is cleared, the actually stored
bytes are not accessible any more and the FiFo buffer can be filled with another 512 bytes
(or 255 bytes if the bit FiFoSize is set to 1) again.
13.4 Status Information about the FiFo buffer
The host may obtain the following data about the FiFo-buffers status:
Number of bytes already stored in the FiFo-buffer: FiFoLength in register
FiFoLength_Reg
Warning, that the FiFo-buffer is almost full: HiAlert in register FiFoControl_Reg
according to the value of the water level in register WaterLevel_Reg (Register 0x02
bit [2], Register 0x03 bit[7:0])
Warning, that the FiFo-buffer is almost empty: LoAlert in register FiFoControl_Reg
FiFoOvl bit indicates, that bytes were written to the FiFo buffer although it was already
full: ErrIrq in register Irq0_Reg. ErrIrq can be cleared only by setting bit FiFoFlash in
the register FiFoControl_Reg.
The CLRC663 can generate an interrupt signal if:
LoAlertIRQEn in register IRQ0En_Reg is set to logic 1 it will activate pin IRQ when
LoAlert in the register FiFoControl_Reg changes to 1.
HiAlertIRQEN in register IRQ0En_Reg is set to logic 1 it will activate pin IRQ when
HiAlert in the register FiFoControl_Reg changes to 1.
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