參數(shù)資料
型號(hào)： M34559G6FP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP52
封裝： 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52
文件頁(yè)數(shù)： 65/93頁(yè)
文件大小： 1810K
代理商： M34559G6FP
CLRC663
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Preliminary data sheet
COMPANY PUBLIC
Rev. 3.1 — 26 September 2011
171131
73 of 126
NXP Semiconductors
CLRC663
Contactless reader IC
A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while SCL is
HIGH.
The master always generates the START and STOP conditions. The bus is considered to
be busy after the START condition. The bus is considered to be free again a certain time
after the STOP condition.
The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In
this respect, the START (S) and repeated START (Sr) conditions are functionally identical.
Therefore, the S symbol will be used as a generic term to represent both the START and
repeated START (Sr) conditions.
10.4.4 Byte format
Each byte has to be followed by an acknowledge bit. Data is transferred with the MSB
bytes during one data transfer is unrestricted but shall fulfil the read/write cycle format.
10.4.5 Acknowledge
An acknowledge at the end of one data byte is mandatory. The acknowledge-related clock
pulse is generated by the master. The transmitter of data, either master or slave, releases
the SDA line (HIGH) during the acknowledge clock pulse. The receiver shall pull down the
SDA line during the acknowledge clock pulse so that it remains stable LOW during the
HIGH period of this clock pulse.
The master can then generate either a STOP (P) condition to stop the transfer, or a
repeated START (Sr) condition to start a new transfer.
A master-receiver shall indicate the end of data to the slave- transmitter by not generating
an acknowledge on the last byte that was clocked out by the slave. The slave-transmitter
shall release the data line to allow the master to generate a STOP (P) or repeated START
(Sr) condition.
Fig 18. START and STOP conditions
001aam301
START condition
S
SCL
SDA
SCL
SDA
STOP condition
P
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