參數(shù)資料
型號(hào): M34559G6FP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP52
封裝: 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52
文件頁(yè)數(shù): 55/93頁(yè)
文件大小: 1810K
代理商: M34559G6FP
CLRC663
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Preliminary data sheet
COMPANY PUBLIC
Rev. 3.1 — 26 September 2011
171131
64 of 126
NXP Semiconductors
CLRC663
Contactless reader IC
9.16.3 RxSyncValH_Reg
9.16.4 RxSyncValL_Reg
9.16.5 RxSyncMod_Reg
Table 193. RxSyncValH_Reg register (address5Ah); reset value: 00h
Bit
7
6
5
4
3
2
1
0
Symbol
RxSyncValH
Access
rights
r/w
Table 194: Description of RxSyncValH_Reg bits
Bit
Symbol
Description
15 to 0
RxSyncValH
Defines the high byte of the Sync Pattern, which must be in front of the
receiving data.
Table 195. RxSyncValL_Reg register (address 5Bh); reset value: 01h
Bit
7
6
5
4
3
2
1
0
Symbol
RxSyncValL
Access
rights
r/w
Table 196: Description of RxSyncValL_Reg bits
Bit
Symbol
Description
7 to 0
RxSyncValL
Defines the low byte of the Sync Pattern, which must be in front of the
receiving data.
Table 197. RxSyncMode register (address 5Ch); reset value: 00h
Bit
7
6
5
4
3
2
1
0
Symbol
SyncLen
SyncNegEdge
LastSyncHalf
SyncType
Access
rights
r/w
Table 198: Description of RxSyncMod_Reg bits
Bit
Symbol
Description
7 to 4
SyncLen
Defines how many Bits of SyncLen are valid.
3
SyncNegEdge Is used for SOF with no correlation peak. The first negative edge of the
correlation is used for defining the bid grid
2
LastSyncHalf
The last Bit of the Sync mode has only half of the length compared to
all other bits. (ISO/IEC18000-3 Mode 3)
1 to 0
SyncType
Set to 0 all 16 bits of SyncVal are interpreted as burst.
Set to 1 a nibble of bits is interpreted as one bit in following way:
{data, coll} data = zero or one; coll = 1 means a collision on this bit.
Note: if Coll = 1 the value of data is ignored.
Set to 2 the synchronisation is done at every start bit of each byte
(type B)
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