參數(shù)資料
型號(hào)： M34559G6FP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP52
封裝： 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52
文件頁(yè)數(shù)： 64/93頁(yè)
文件大小： 1810K
代理商： M34559G6FP
CLRC663
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Preliminary data sheet
COMPANY PUBLIC
Rev. 3.1 — 26 September 2011
171131
72 of 126
NXP Semiconductors
CLRC663
Contactless reader IC
interface can only act in Slave mode. Therefore no clock generation and access
arbitration is implemented in the CLRC663. High speed mode is not supported by the
CLRC663
10.4.1 General
The implemented interface is compatible to the “I2C-bus specification version 3.0, June
2007”. The CLRC663 can act as a slave receiver or slave transmitter in Standard mode,
Fast mode and Fast Mode Plus.
SDA is a bidirectional line, connected to a positive supply voltage via a pull-up resistor.
Both lines SDA and SCL are set to HIGH level if no data is transmitted. The CLRC663 has
a tri-state output stage to perform the wired-AND function. Data on the I2C-bus can be
transferred at data rates of up to 400 kbit/s in Fast mode, up to 1 Mbit/s in the Fast Mode
Plus.
If the I2C interface is selected, a spike suppression according to the I2C interface
specification on SCL and SDA is activated.
10.4.2 Data validity
Data on the SDA line shall be stable during the HIGH period of the clock. The HIGH or
LOW state of the data line shall only change when the clock signal on SCL is LOW.
10.4.3 START and STOP conditions
To handle the data transfer on the I2C-bus, unique START (S) and STOP (P) conditions
are defined.
A START condition is defined with a HIGH-to-LOW transition on the SDA line while SCL is
HIGH.
Fig 16. I2C-bus interface
001aam000
CLRC663
SDA
SCL
PULL-UP
NETWORK
PULL-UP
NETWORK
MICROCONTROLLER
Fig 17. Bit transfer on the I2C-bus.
001aam300
data line stable;
data valid
change
of data
allowed
SDA
SCL
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