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| 型號： | M34559G6FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52 |
| 文件頁數(shù)： | 79/93頁 |
| 文件大小： | 1810K |
| 代理商： | M34559G6FP |
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CLRC663
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Preliminary data sheet
COMPANY PUBLIC
Rev. 3.1 — 26 September 2011
171131
86 of 126
NXP Semiconductors
CLRC663
Contactless reader IC
11.3.2 Block diagram
Figure 27 shows the block diagram of the receiver circuitry. The receiving process
includes several steps. First the quadrature demodulation of the carrier signal of
13.56 MHz is done. Several tuning steps in this circuit are possible.
The receiver can also be used as single ended solution. In this case only one side has to
be assembled and the Rcv_RX_single has to be set. In the single ended use case two
receiver pins have to be connected.
Remark: When using the receiver single ended the reading distance will be influenced
because of decreased sensitivity as well as the noise immunity.
The quadrature-demodulator uses two different clocks, Q-clock and I-clock, with a phase
shift of 90
between them. Both resulting baseband signals are amplified, filtered and
forwarded to a correlation circuitry.
11.4 S3C interface / (GPIO0)SigIn-SigOut
Two main blocks are implemented in the CLRC663. A digital circuitry, comprising state
machines, coder and decoder logic and an analog circuitry with the modulator and
antenna drivers, receiver and amplification circuitry. For example, the interface between
these two blocks can be configured in the way, that the interfacing signals may be routed
to the pins (GPIO0)SigIn and SigOut. The most important use of this topology is the active
Fig 27. Block diagram of receiver circuitry
Table 222. Usage of single or differential receiver
Mode
rcv_rx_single
pins rx_p and rx_n
Fully differential
0
provide differential signal from
differential antenna by separate
rx-coupling branches
Quasi differential
1
connect RXP and RXN together
and provide single ended signal
from antenna by a single
rx-coupling branch
001aan358
13.56 MHz
I/O CLOCK
GENERATION
I-clks
Q-clks
clk_27 MHz
TIMING
GENERATION
ADC
Adc_data_ready
clk_27 MHz
mixer
mix_out_i_p
2-stage BBA
mix_out_i_n
out_i_p
6-BIT 6.78MS DATA
out_i_n
rx_p
rx_n
rx_p
rx_n
mixer
mix_out_q_p
2-stage BBA
mix_out_q_n
out_q_p
6-BIT 6.78MS DATA
out_q_n
rcv_gain<1:0>
rcv_hpcf<1:0>
fully/quasi-differential
rcv_gain<1:0>
rcv_hpcf<1:0>
rx_p
rx_n
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