參數(shù)資料
型號： M34559G6FP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP52
封裝： 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52
文件頁數(shù)： 57/93頁
文件大小： 1810K
代理商： M34559G6FP
CLRC663
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Preliminary data sheet
COMPANY PUBLIC
Rev. 3.1 — 26 September 2011
171131
66 of 126
NXP Semiconductors
CLRC663
Contactless reader IC
9.16.8 FabCali_Reg
9.17 Description/Version register
9.17.1 Version_Reg
10. DIGITAL interfaces
10.1
Microcontroller interface type
The CLRC663 supports direct interfacing of various hosts as the SPI, I2C, I2CL and serial
UART interface type. The CLRC663 resets its interface and checks the current host
interface type automatically having performed a Power-On or Hard Reset. The CLRC663
identifies the host interface by the means of the logic levels on the control pins after the
Reset Phase. This is done by a combination of fixed pin connections.The following table
shows the different configurations:
Table 203:
FabCali_Reg register (address 5Fh); reset value: B2h
Bit
7
6
5
4
3
2
1
0
Symbol
FabCali
Access
rights
r/w
Table 204: Description of FabCali_Reg bits
Bit
Symbol
Description
7 to 0
FabCali
Fab calibration of the receiver
NOTE: do not change boot value
Table 205. Version_Reg register (address 7Fh); reset value: 10h
Bit
7
6
5
4
3
2
1
0
Symbol
Version
SubVersion
Access
rights
rr
Table 206: Version_Reg bits
Bit
Symbol
Description
7 to 4
Version
Includes the version of the CLRC663
3 to 0
SubVersion
Includes the subversion of the CLRC663
Table 207: Connection Scheme for detecting the different Interface Types
UART
SPI
I2C
I2C-L
IF0
I/O
Rx
MOSI
ADR1
IF1(SCL)
I/O
-
SCK
SCL
IF2
I/O
TX
MISO
ADR2
SDA
IF3(SDA)
I/O
Trigger
NSS
SDA
ADR2
IF1SEL0
I
0
1
IF1SEL1
I
0
1
0
1
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