參數(shù)資料
型號: M34559G6FP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP52
封裝: 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52
文件頁數(shù): 67/93頁
文件大小: 1810K
代理商: M34559G6FP
CLRC663
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Preliminary data sheet
COMPANY PUBLIC
Rev. 3.1 — 26 September 2011
171131
75 of 126
NXP Semiconductors
CLRC663
Contactless reader IC
10.4.7 Register Write Access
To write data from the host controller via I2C to a specific register of the CLRC663 the
following frame format shall be used.
The first byte of a frame indicates the device address according to the I2C rules. The
second byte indicates the register address followed by up to n-data bytes. In one frame all
n-data bytes are written to the same register address. This enables for example a fast
FiFo access.
The read/write bit shall be set to logic 0.
10.4.8 Register Read Access
To read out data from a specific register address of the CLRC663 the host controller shall
use the procedure:
First a write access to the specific register address has to be performed as indicated in the
following frame.
The first byte of a frame indicates the device address according to the I2C rules. The
second byte indicates the register address. No data bytes are added.
The read/write bit shall be logic 0.
Having performed this write access, the read access can start. The host has to send the
device address of the CLRC663. As an answer to this the CLRC663 responds with the
content of this register. In one frame all n-data bytes could be read from the same register
address. This enables for example a fast FiFo access or register polling.
NOTE: When writing the sequence [address byte][data1][data2][data3]..., [data1] is written
to address [address byte], [data2] is written to address [address byte + 1] and [data3] is
written to [address byte + 2].
Exception: This auto increment of the address byte is not valid for writing data to the FiFo
The read/write bit shall be set to logic 1.
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