參數(shù)資料
型號(hào)： M34559G6FP
元件分類(lèi)： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP52
封裝： 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52
文件頁(yè)數(shù)： 68/93頁(yè)
文件大小： 1810K
代理商： M34559G6FP
CLRC663
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Preliminary data sheet
COMPANY PUBLIC
Rev. 3.1 — 26 September 2011
171131
76 of 126
NXP Semiconductors
CLRC663
Contactless reader IC
10.4.9 I2CL Bus Interface
The CLRC663 provides an additional interface according of a logical handling of an I2C
interface. This logical interface fulfills in general the I2C specification, but all timing related
factor will not be according the standard. Standard I/O pad are used for communication
and the communication speed is limited to 5 Mbaud. The protocol itself is equivalent to the
FAST mode protocol of I2C. The Interphase address is 01010xxb, where the last two bit of
the address can be defined by the application. To define this two bit there are basically two
possibilities. Defining it with a pin, where the higher bit is fixed to 0 or the configuration is
fixed via EEPROM. Refer to the EEPROM configuration in Section 12.
The output of this interface port is an asynchronous parallel port with two control lines,
read (rd) and write (wr). The Write access is synchronized in the host interface module.
Fig 22. Register read and write access
001aam305
Ack
0
(W)
Ack
0
SA
I2C slave address
A7-A0
CLRC663 register
address A6-A0
Ack
DATA
[7..0]
SO
[0..n]
Ack
0
(W)
Ack
Optional, if the previous access was on the same register address
Read Cycle
Write Cycle
0
SA
I2C slave address
A7-A0
CLRC663 register
address A6-A0
1
(R)
Ack
SA
sent by master
sent by slave
I2C slave address
A7-A0
Ack
DATA
[7..0]
SO
[0..n]
0..n
Nack
DATA
[7..0]
Table 217. Timing parameter I2CL
Parameter
Min
Max
Unit
fSCL
05MHz
tHD;STA
80
-
ns
tLOW
100
-
ns
tHIGH
100
-
ns
tSU;SDA
80
-
ns
tHD;DAT
050
ns
tSU;DAT
020
ns
tSU;STO
80
-
ns
tBUF
200
-
ns
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