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| 型號： | M34559G6FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52 |
| 文件頁數(shù)： | 69/93頁 |
| 文件大小： | 1810K |
| 代理商： | M34559G6FP |
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CLRC663
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Preliminary data sheet
COMPANY PUBLIC
Rev. 3.1 — 26 September 2011
171131
77 of 126
NXP Semiconductors
CLRC663
Contactless reader IC
10.4.10 I2CLSAM Bus Interface
The CLRC663 provides an additional I2C interface. This logical interface fulfills in general
the I2C specification, but all timing related factors will not be according the standard. Refer
to I2CL. To use this interface the configuration has to be defined via EEPROM. (Refer to
One major difference between I2C and I2CL is the missing pull-up resistor. The driver of
the pad must push the line to the desired logic voltage. To avoid that two drivers are
pushing the line at the same time following regulations must be fulfilled:
SCL: As there is no clock stretching allowed the SCL is always under control of the
Master. A buskeeper structure is not required.
SDA: The SDA line is shared between master and slave. Therefore the master and the
slave must have the control over the own driver enable line of the SDA pad. Following
rules must be followed:
In the IDLE phase the SDA line is driven HIGH by the MASTER
In the time between START and STOP condition the SDA line is driven by MASTER
or SLAVE when SCL is LOW. If SCL is HIGH the SDA line is not driven by any device
To keep the value on the SDA line a buskeeper structure is needed for the line
10.5 Boundary Scan
The CLRC663 provides a boundary scan interface according the IEEE 1149.1. This
interface provides a possibilities to test interconnections without using physical test
probes. This is done by “test cells”, connected to each pin, which overrides the
functionality of this pin.
To be able to program the “test cells” the following commands are supported:
The Standard IEEE 1149.1 describes the four basic blocks necessary to use this interface:
Test Access Port (TAP); TAP controller; - Instruction register, - Data register;
Table 218. Boundary Scan command
Value
Command
Parameter in
Parameter out
0h
bypass
-
7h
1h
preload
data (Pin)
-
1h
sample
-
data (Pin)
2h
ID code (default)
-
data (32)
3h
USER code
-
data (32)
4h
clamp
-
5h
HIGH Z
-
7h
extest
data (pin)
8h
interface on/off
interface (8)
-
9h
register access read
address (7)
data
Ah
register access write
address (7) - data (8)
-
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