參數(shù)資料
型號(hào)： M34559G6FP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP52
封裝： 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52
文件頁數(shù)： 80/93頁
文件大小： 1810K
代理商： M34559G6FP
CLRC663
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Preliminary data sheet
COMPANY PUBLIC
Rev. 3.1 — 26 September 2011
171131
87 of 126
NXP Semiconductors
CLRC663
Contactless reader IC
antenna concept where the digital and the analog part are ideologically separated. This
opens the possibility to connect e.g. an additional digital part of another device with the
one analog antenna front-end.
The Table 223 and Table 224 shows the necessary register configuration for the use case
active antenna concept.
The interface between these two blocks can be configured in the way, that the interfacing
signals may be routed to the pins SIGIN and SIGOUT (see Figure 29 “Overview
(GPIO0)SIGIN/SIGOUT Signal Routing”). The configuration is done by bits MFOutSel,
TxSel and UARTSel of registers TxSelReg and RxSelReg.
This topology supports, that some parts of the analog part of the CLRC663 may be
connected to the digital part of another device.
The switch MFOutSel in register TxSelReg can be used to measure MIFARE and
ISO/IEC14443 related signals. This is especially important during the design In phase or
for test purposes to check the transmitted and received data.
However, the most important use of MFIN/MFOUT pins is the active antenna concept. An
external active antenna circuit can be connected to the digital circuit of the CLRC663.
MFOutSel has to be configured in that way that the signal of the internal Miller Coder is
send to MFOUT pin (MFOutSel = 4). UARTSel has to be configured to receive
Manchester signal with sub-carrier from MFIN pin (UARTSel = 1).
It is possible, to connect a 'passive antenna' to pins TX1, TX2 and RX (via the appropriate
filter and matching circuit) and at the same time an Active Antenna to the pins MFOUT
and MFIN. In this configuration, two RF-parts may be driven (one after another) by one
host processor.
Fig 28. Block diagram of the active Antenna concept
Table 223. Register configuration of CLRC663 active antenna concept (DIGITAL)
Register
Value
Description
SigOut.SigOutSel
0100h
TxEnvelope
Rcv.sigpro_in_sel
10
11
Receive over SigIn (ISO/IEC14443A)
Receive over SigIn (Generic Code)
DrvCon.TxSel
00
Low (idle)
Table 224. Register configuration of CLRC663 active antenna concept (Antenna)
Register
Value
Description
SigOut.SigOutSel
0110h
0111h
Generic Code (Manchester)
Manchester with Subcarrier (ISO/IEC14443A)
Rcv.sigpro_in_sel
01
Internal
DrvCon.TxSel
10
External (SigIn)
RxCtrl.RxMultiple
1
RxMultiple on
001aam307
SIGIN
SIGOUT
CLRC663
(DIGITAL)
CLRC663
(ANTENNA)
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