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參數(shù)資料
| 型號： | M34559G6FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52 |
| 文件頁數(shù)： | 47/93頁 |
| 文件大?。?/td> | 1810K |
| 代理商： | M34559G6FP |
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CLRC663
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Preliminary data sheet
COMPANY PUBLIC
Rev. 3.1 — 26 September 2011
171131
57 of 126
NXP Semiconductors
CLRC663
Contactless reader IC
9.15.3 TxDataMOD_Reg
9.15.4 TxSymFreq_Reg
Table 163. TxDataMod_Reg register (address 4Bh); reset value:04h
Bit
7
6
5
4
3
2
1
0
Symbol
Frame step
DMillerEn
DPulseType
DInvert
DEnvType
Access
rights
r/w
Table 164: Description of TxDataMod_Reg bits
Bit
Symbol
Description
7
Framestep
If set to 1, at every start of transmission, each byte of data is sent in a
separate frame. SOF and EOF is appended to the data byte according
to the framing settings. After one byte is transmitted, the TxEncoder
waits for a new start trigger to continue with the next byte (trigger is
generated automatically). If set to 0, transmission is done in the used
way, where after a start trigger all data bytes are sent and the framing
is done for the complete data stream only once.
6
DMillerEn
If set to 1, pulse modulation is applied according to modified miller
code.
Note: This bit shall only be set if DPulseType is set to 01(bin)
5 to 4
DPulseType
Specifies which type of pulse modulation is selected.
00b: no pulse modulation
01b: pulse starts at beginning of bit
10b: pulse starts at beginning of second bit half
11b: pulse starts at beginning of third bit quarter
Note: If DMillerEn is set to 1, DPulseType must be set to 01b
3
DInvert
If set to 1, the output envelope is inverted.
2 to 0
DEnvType
Specifies the type of envelope used for transmission of data packets.
The selected envelope type is applied to the pseudo bit stream.
000b: Direct output
001b: Manchester code
010b: Manchester code with subcarrier
011b: BPSK
100b: RZ (pulse of half bit length at beginning of second half of bit)
101b: RZ (pulse of half bit length at beginning of bit)
110b: RFU
111b: RFU
Table 165. TxSymFreq_Reg (address 4Ch); reset value: 50h
Bit
7
6
5
4
3
2
1
0
Symbol
S32SC
Freq
S32BFreq
S10SC
Freq
S10B
Freq
Access
rights
r/w
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| M34559G6-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
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