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參數資料
| 型號： | M34559G6FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52 |
| 文件頁數： | 8/93頁 |
| 文件大小： | 1810K |
| 代理商： | M34559G6FP |
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CLRC663
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Preliminary data sheet
COMPANY PUBLIC
Rev. 3.1 — 26 September 2011
171131
105 of 126
NXP Semiconductors
CLRC663
Contactless reader IC
The following data shall be written to the FiFo before the command can be activated:
LoadKeyE2
Authentication command code (60h, 61h)
Block address
Card serial number byte 0
Card serial number byte 1
Card serial number byte 2
Card serial number byte 3
In total, 12 bytes are written to the FiFo.
Remark: When the MFAuthent command is active, any FiFo access is blocked. If there is
an attempt to access to the FiFo during MFAuthent beeing active, the bit WrErr in the
ErrorReg register is set.
This MFAuthent command terminates automatically when the MIFARE card is
authenticated and the bit MFCrypto1On in the Status_Reg register is set to logic 1.
This MFAuthent command does not terminate automatically when the card does not
answer, therefore the timer should be initialized to automatic mode. In this case, beside
the bit IdleIrq, the bit TimerIrq can be used as termination criteria. During authentication
processing the bit RxIrq and bit TxIrq are blocked. The Crypto1On bit is only valid after
termination of the authentication command (either after processing the protocol or after
writing IDLE to the command register).
In case there is an error during authentication, the bit ProtocolErr in the ErrorReg register
is set to logic 1 and the bit Crypto1On in register Status2Reg is set to logic 0.
18.3.1.5
Ack Reqcommand
Performs a Query (Full command must be written into the FiFo); a Ack and a ReqRn
command. All answer of the command will be written into the FiFo. The error flag is copied
after the answer into the FiFo.
This command terminates automatically when finished and the active command is idle.
18.3.1.6
Receive command
The CLRC663 activates the receiver path and waits for any data stream to be received.
The correct settings have to be chosen before starting this command.
This command terminates automatically when the received data stream ends. This is
indicated either by the end of frame pattern or by the length byte depending on the
selected framing and speed.
Remark: If the bit RxMultiple in the RxModeReg register is set to logic 1, the Receive
command does not terminate automatically. It has to be terminated by activating any other
command in the CommandReg register (see Section 9.16.6 “RxMod_Reg”).
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