參數(shù)資料
型號(hào)： M34559G6FP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP52
封裝： 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52
文件頁(yè)數(shù)： 70/93頁(yè)
文件大小： 1810K
代理商： M34559G6FP
CLRC663
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Preliminary data sheet
COMPANY PUBLIC
Rev. 3.1 — 26 September 2011
171131
78 of 126
NXP Semiconductors
CLRC663
Contactless reader IC
10.5.1 Test Access Port (TAP)
The access port is the interface between the Chip and the environment. There are three
Inputs: Test Clock (TCK); Test mode Select (TMS); Test Data Input (TDI) and one Output:
Test Data Output.TCK and TMS are broadcast signals, TDI to TDO generate a serial line
called Scan path.
Advantage of this technique is that independent of the numbers of boundary scan devices
the complete path can be handled with four signal lines.
The signals TCK, TMS are directly connected with the TAP controller. Because these
signals are responsible for the mode of the chip, all boundary scan devises in one scan
path will be in the same TAP mode.
10.5.2 Test Clock (TCK)
The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can
operate independently of any other system clocks. In addition, it ensures that multiple
JTAG TAP controllers that are daisy-chained together can synchronously communicate
serial test data between components. During normal operation, TCK is driven by a
free-running clock with a nominal 50 % duty cycle. When necessary, TCK can be stopped
at 0 or 1 for extended periods of time. While TCK is stopped at 0 or 1, the state of the TAP
controller does not change and data in the JTAG Instruction and Data Registers is not lost.
By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures
that no clocking occurs if the pin is not driven from an external source. The internal pull-up
and pull-down resistors can be turned off to save internal power as long as the TCK pin is
constantly being driven by an external source.
10.5.3 Test Mode Select (TMS)
The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the
rising edge of TCK. Depending on the current TAP state and the sampled value of TMS,
the next state is entered. Because the TMS pin is sampled on the rising edge of TCK, the
IEEE Standard 1149.1 expects the value on TMS to change on the falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine
to the Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state,
the JTAG Instruction Register (IR) resets to the default instruction, IDCODE. Therefore,
this sequence can be used as a reset mechanism, similar to asserting TRST.
By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to
the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor
remains enabled on PC1/TMS; otherwise JTAG communication could be lost an path.
10.5.4 Test Data Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI
is sampled on the rising edge of TCK and, depending on the current TAP state and the
current instruction, presents this data to the proper shift register chain. Because the TDI
pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on
TDI to change on the falling edge of TCK.
By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to
the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor
remains enabled on PC2/TDI; otherwise JTAG communication could be lost
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