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| 型號： | M34559G6FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52 |
| 文件頁數(shù)： | 59/93頁 |
| 文件大?。?/td> | 1810K |
| 代理商： | M34559G6FP |
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CLRC663
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Preliminary data sheet
COMPANY PUBLIC
Rev. 3.1 — 26 September 2011
171131
68 of 126
NXP Semiconductors
CLRC663
Contactless reader IC
10.2.3 Write data
To write data to the CLRC663 using the SPI interface the following byte order has to be
used. It is possible to write out up to n-data bytes by only sending one’s address byte.
The first send byte defines both, the mode itself and the address byte.
Remark: The most significant bit (MSB) has to be send first.
10.2.4 Address byte
The address byte has to fulfil the following format:
The LSB bit of the first byte defines the used mode. To read data from the CLRC663 the
LSB bit is set to logic 1. To write data to the CLRC663 the MSB bit has to be set to logic 0.
The bits 6 to 0 define the address byte.
NOTE: When writing the sequence [address byte][data1][data2][data3]..., [data1] is written
to address [address byte], [data2] is written to address [address byte + 1] and [data3] is
written to [address byte + 2].
Exception: This auto increment of the address byte is not valid for writing data to the FiFo
10.2.5 Timing Specification SPI
The timing conditions for SPI interface is as follow:
Table 209: Byte Order for MOSI and MISO
byte 0
byte 1
byte 2
to
byte n
byte n + 1
MOSI
address 0
data 0
data 1
……..
data n
1
data n
MISO
X
……..
X
Table 210. Address byte 0 register; address MOSI
7
6
5
4
3
2
1
0
address 6
address 5
address 4
address 3
address 2
address 1
address 0
1 (read)
0 (write)
MSB
LSB
Table 211. Timing conditions SPI
Symbol
Parameter
Conditions
Min
Typ
Max Unit
tSCKL
SCK LOW time
VDD(PVDD) VDDA = VDDD = VDD(TVDD);
VSSA =VSSD =VSS(PVSS) =VSS(TVSS) =0V
50
--ns
tSCKH
SCK HIGH time
VDD(PVDD) VDDA = VDDD = VDD(TVDD);
VSSA =VSSD =VSS(PVSS) =VSS(TVSS) =0V
50
ns
th(SCKH-D)
SCK HIGH to data input hold
time
SCK to changing MOSI;
VDD(PVDD) VDDA =VDDD = VDD(TVDD);
VSSA =VSSD =VSS(PVSS) =VSS(TVSS) =0V
25
ns
tsu(D-SCKH)
data input to SCK HIGH set-up
time
changing MOSI to SCK;
VDD(PVDD) VDDA =VDDD =VDD(TVDD);
VSSA =VSSD =VSS(PVSS) =VSS(TVSS) =0V
25
ns
th(SCKL-Q)
SCK LOW to data output hold
time
SCK to changing MISO;
VSSA =VSSD =VSS(PVSS) =VSS(TVSS) =0V
-25
ns
t(SCKL-NSSH) SCK LOW to NSS HIGH time
0
ns
tNSSH
NSS HIGH time
before communication
50
-
ns
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