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SERIAL INTERFACE
12
12-26
32185/32186 Group Hardware Manual
Rev.1.10 REJ09B0235-0110 May 15, 07
12.2 Serial Interface Related Registers
Table 12.2.2 Example Settings of the SIO Baud Rate Register (UART Mode) (1/2)
items
When clock divider count source = 8MHz
When clock divider count source = 10MHz
Band
Clock divider
BRG A margin Actual baud rate
Clock divider
BRG
A margin
Actual baud rate
rate
divide value
set
of error
[bps]
divide value
set
of error
[bps]
[divided-by n]
value
(%)
[divided-by n]
value
(%)
300
32
51
0.16
300.48
32
64
0.16
300.48
600
32
25
0.16
600.96
8
129
0.16
600.96
1200
32
12
0.16
1201.92
8
64
0.16
1201.92
2400
-
8
32
-1.36
2367.42
4800
1
103
0.16
4807.69
1
129
0.16
4807.69
9600
1
51
0.16
9615.38
1
64
0.16
9615.38
14400
1
34
-0.79
14285.71
1
42
0.94
14534.88
19200
1
25
0.16
19230.77
1
32
-1.36
18939.39
38400
1
12
0.16
38461.54
1
15
1.73
39062.50
57600
-
1
10
-1.36
56818.18
115200
-
128000
-
250000
1
0.00
250000.00
-
500000
1
0
0.00
500000.00
-
625000
-
1
0
0.00
625000.00
1000000
-
1250000
-
Notes: This does not mean that the communication at the above baud rates is guaranteed. Careful consideration and
inspection under your environment are required before use.
Select clock divider count source in SELCLK bit of SIOn special mode register (SnSMOD).
Select divide-by value of clock divider in the CDIV bit of SIOn transmit control register (SnTCNT).
Set BRG set value in the SIOn baud rate register (SnBAUR).
Table 12.2.2 Example Settings of the SIO Baud Rate Register (UART Mode) (2/2)
items
When clock divider count source = 16MHz
When clock divider count source = 20MHz
Band
Clock divider
BRG
A margin
Actual baud rate
Clock divider
BRG A margin Actual baud rate
rate
divide value
set
of error
[bps]
divide value
set
of error
[bps]
[divided-by n]
value
(%)
[divided-by n]
value
(%)
300
32
103
0.16
300.48
32
129
0.16
300.48
600
32
51
0.16
600.96
32
64
0.16
600.96
1200
32
25
0.16
1201.92
32
-1.36
1183.71
2400
32
12
0.16
2403.85
32
15
1.73
2441.41
4800
1
207
0.16
4807.69
1
259
0.16
4807.69
9600
1
103
0.16
9615.38
1
129
0.16
9615.38
14400
1
68
0.64
14492.75
1
86
-0.22
14367.82
19200
1
51
0.16
19230.77
1
64
0.16
19230.77
38400
1
25
0.16
38461.54
1
32
-1.36
37878.79
57600
-
1
21
-1.36
56818.18
115200
-
1
10
-1.36
113636.36
128000
-
250000
1
3
0.00
250000.00
1
4
0.00
250000.00
500000
1
0.00
500000.00
-
625000
-
1
0.00
625000.00
1000000
1
0
0.00
1000000.00
-
1250000
-
1
0
0.00
1250000.00
Notes: This does not mean that the communication at the above baud rates is guaranteed. Careful consideration and
inspection under your environment are required before use.
Select clock divider count source in SELCLK bit of SIOn special mode register (SnSMOD).
Select divide-by value of clock divider in the CDIV bit of SIOn transmit control register (SnTCNT).
Set BRG set value in the SIOn baud rate register (SnBAUR).