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型號：	M32185F4VFP
元件分類：	微控制器/微處理器
英文描述：	32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
封裝：	20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù)：	349/1032頁
文件大?。?/td>	5750K
代理商：	M32185F4VFP

10.3 TOP (Output-Related 16-Bit Timer)

MULTIJUNCTION TIMERS

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

10.3.11 Operation in TOP Continuous Output Mode (without Correction Function)

(1) Outline of TOP continuous output mode

In continuous output mode, the timer counts down starting from the set value of the counter and at the cycle

after the counter underflows, it is loaded with the value that " the reload register -1." Thereafter, this opera-

tion is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is

inverted in width of " reload register set value + 1."

When the timer is enabled (by writing to the enable bit in software or by external input) after setting the

counter and reload register, it starts counting down from the counter’s set value synchronously with the

count clock and when the minimum count is reached, generates an underflow.

At the cycle after this underflow, the counter to be loaded with the content of " the reload register -1" and

count down over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the

counter, disable count by writing to the enable bit in software.

The F/F output waveform in continuous output mode is inverted (F/F output level changes from "L" to "H" or

vice versa) at startup and upon underflow, generating a waveform of consecutive pulses until the timer

stops counting. An interrupt request can be generated each time the counter underflows.

The " counter set value + 1" and " reload register set value + 1" are effective as count values.

For example, if the initial counter value is 4 and the initial reload register value is 5, then the timer operates

as shown below.

Figure 10.3.17 Example of Counting in TOP Continuous Output Mode

Interrupt request

Note 1: What actually is seen in the cycle immediately during enable is the previous counter value, and not 4.

Note 2: What actually is seen in the cycle immediately during underflow is H'FFFF (underflow value), and not 5.

Note 3: The value that "reload register - 1" is reloaded.

Note: This diagram does not show detailed timing information.

dependent delay

Count value = 5

Count value = 6

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