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型號：	M32185F4VFP
元件分類：	微控制器/微處理器
英文描述：	32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
封裝：	20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù)：	471/1032頁
文件大?。?/td>	5750K
代理商：	M32185F4VFP

10.8 TOU (Output-Related 24-Bit Timer)

MULTIJUNCTION TIMERS

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

(3) Using the pin level on ports P87(P00)/TO21–P82(P05)/TO26 or P110(P10)/TO29–P115(P15)/TO34 to

disable PWM outputs

The pin level ("H" or "L") on ports P87(P00)/TO21–P82(P05)/TO26 may be used to disable outputs from the

ports P87(P00)/TO21–P82(P05)/TO26 that are provided for the PWM outputs of the timer TOU0_0–

TOU0_5. Similarly, the pin level ("H" or "L") on ports P110(P10)/TO29–P115(P15)/TO34 may be used to

disable outputs from the ports P110(P10)/TO29–P115(P15)/TO34 that are provided for the PWM outputs of

the timer TOU1_0–TOU1_5 .

After detecting PWM output disable level from port P87(P00)/TO21–P82(P05)/TO26, P110(P10)/TO29–

P115(P15)/TO34, PWM output is disabled. During PWM Output Disable, POnDISGmbit of PWM output n

disable control Gm register is set as "1."

Restoring output enable status is done by exiting outputting PWM output disable level from port P87(P00)/

TO21–P82(P05)/TO26, P110(P10)/TO29–P115(P15)/TO34 and then by '0' clearing POnDISGmbit of PWM

output n disable Gm register (POnDISGmCR ).

Note: If POnDISGmbit in PWM output n disable control Gm register is written during PWM Out-

put Disable level outputting from port P87(P00)/TO21–P82(P05)/TO26, P110(P10)/

TO29–P115(P15)/TO34, that operation of writing has no effect.

To disable PWM outputs using the pin level of ports, set up the PWM Output Disable Level Control Register

(POnLVGACR, POnLVGBCR) and PWMOFF Function Enable Register (PWMOFFnEN) as described below.

When using the P87(P00)/TO21–P82(P05)/TO26 port level to disable PWM outputs

1. Using the PO0LVGACR(PO0LVGBCR) register PO0LVSELGA(PO0LVSELGB) bit, select the "H" or "L"

level at which PWM output is to be disabled.

2. Set the PO0LVENGA(PO0LVENGB) bit to "1" (the selected output disable level effective).

3. Enable the PWMOFF0 function by writing "1" to either or both of the PWMOFF0GAEN and

PWMOFF0GBEN bits of the PWMOFF0EN.

When using the P110(P10)/TO29–P115(P15)/TO34 port level to disable PWM outputs

1. Using the PO1LVGACR(PO1LVGBCR) register PO1LVSELGA(PO1LVSELGB) bit, select the "H" or

"L" level at which PWM output is to be disabled.

2. Set the PO1LVENGA(PO1LVENGB) bit to "1" (the selected output disable level effective).

3. Enable the PWMOFF1 function by writing "1" to either or both of the PWMOFF1GAEN and

PWMOFF1GBEN bits of the PWMOFF1EN.

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