1
OVERVIEW
1-14
32185/32186 Group Hardware Manual
Rev.1.10 REJ09B0235-0110 May 15, 07
The pins directed for input go to a high-impedance state (Hi-Z) when reset. The term “when reset” means
that input on RESET# pin is held “L” (the device remains reset), and that the RESET# pin is released back
“H” (the device comes out of reset).
Table 1.4.1 Pin Assignments of the 32185/32186 Group (1/4)
Note1: The pins are outputted at two places.
-
Function
P221
P225
A12
VSS
XIN
XOUT
VCC-BUS
P224
A11
P30
A15
P31
A16
P32
A17
P33
A18
P34
A19
P35
A20
P36
A21
P37
A22
P20
A23
P21
A24
P22
A25
P23
A26
VCC-BUS
VSS
P24
A27
P25
A28
P26
A29
P27
A30
P00
DB0
Type
Input
Output
-
Input
Output
-
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
-
Input
Output
Input
Output
Input
Output
Input
Output
Input
Input/output
State
during reset
Hi-Z
-
XOUT
-
Hi-Z
-
Hi-Z
State upon
exitingreset
Hi-Z
Undefined
-
XOUT
-
Hi-Z
Undefined
Hi-Z
Undefined
Hi-Z
Undefined
Hi-Z
Undefined
Hi-Z
Undefined
Hi-Z
Undefined
Hi-Z
Undefined
Hi-Z
Undefined
Hi-Z
Undefined
Hi-Z
Undefined
Hi-Z
Undefined
Hi-Z
Undefined
Hi-Z
Undefined
-
Hi-Z
Undefined
Hi-Z
Undefined
Hi-Z
Undefined
Hi-Z
Undefined
Hi-Z
-
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
Condition
Function
Pin state when reset
Symbol
Function 2
HREQ#(Note1)
TO21(Note1)
CS2#(Note1)
TIN30
TIN31
TIN32
TIN33
CS3#(Note1)
TIN4
TIN5
TIN6
TIN7
Port
P221
-
P224
P30
P225
P31
P32
P34
P33
P35
P36
P20
P37
P21
P22
P24
P23
P25
P26
P00
P27
Function 1
CRX0(Note1)
VSS
XIN
XOUT
VCC-BUS
VSS
A11
A15
A12
A16
A17
A19
A18
A20
A21
A23
A22
A24
A25
A27
A26
A28
A29
DB0
A30
1
3
4
5
6
20
21
7
Pin
No.
2
8
9
10
11
12
13
14
15
16
17
18
19
22
23
24
25
26
P221/CRX0/HREQ#
VSS
XIN
XOUT
VCC-BUS
VSS
P224/A11/CS2#
P225/A12/CS3#
P30/A15/TIN4/DD16
P31/A16/TIN5/DD17
P32/A17/TIN6/DD18
P33/A18/TIN7/DD19
P34/A19/TIN30/DD20
P35/A20/TIN31/DD21
P36/A21/TIN32/DD22
P37/A22/TIN33/DD23
P20/A23/DD24
P21/A24/DD25
P22/A25/DD26
P23/A26/DD27
P24/A27/DD28
P25/A28/DD29
P26/A29/DD30
P27/A30/DD31
P00/DB0/TO21/DD0
-
Power
supply
VCC-BUS
Input
-
Input
Output
-
Type
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
DRI function
NBD function
-
DD16
-
DD19
DD17
DD18
DD20
DD23
DD21
DD22
DD24
DD27
DD25
DD26
DD28
DD0(Note1)
DD29
DD30
DD31
-
1.4 Pin Assignments