![](http://datasheet.mmic.net.cn/110000/M32186F8VFP_datasheet_3496152/M32186F8VFP_33.png)
1
OVERVIEW
1-15
32185/32186 Group Hardware Manual
Rev.1.10 REJ09B0235-0110 May 15, 07
Table 1.4.1 Pin Assignments of the 32185/32186 Group (2/4)
Note1: The pins are outputted at two places.
DRI function
NBD function
State
during reset
State upon
exiting
42
AVCC0
43
-
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
Symbol
Type
31
32
33
34
35
-
TO35(Note1)
TO36(Note1)
TO31(Note1)
TO32(Note1)
TO33(Note1)
TO34(Note1)
TO24(Note1)
TO25(Note1)
TO26(Note1)
TO27(Note1)
TO22(Note1)
TO23(Note1)
TO28(Note1)
TO29(Note1)
TO30(Note1)
37
36
39
38
40
41
28
Pin
No.
27
29
30
VREF0
AVCC0
AD0IN0
AD0IN1
AD0IN2
AD0IN3
AD0IN4
AD0IN5
AD0IN6
AD0IN7
AD0IN8
AD0IN9
AD0IN10
AD0IN11
AD0IN12
AD0IN13
AD0IN14
AD0IN15
P05/DB5/
TO26/DD5
P06/DB6/
TO27/DD6
P07/DB7/
TO28/DD7
P10/DB8/
TO29/DD8
P11/DB9/
TO30/DD9
P13/DB11/
TO32/DD11
P12/DB10/
TO31/DD10
P15/DB13/
TO34/DD13
P14/DB12/
TO33/DD12
P16/DB14/
TO35/DD14
P17/DB15/
TO36/DD15
P02/DB2/
TO23/DD2
P01/DB1/
TO22/DD1
P03/DB3/
TO24/DD3
P04/DB4/
TO25/DD4
Pin state when reset
Power
supply
VCC-BUS
AVCC0
Function
-
DD5(Note1)
DD6(Note1)
DD7(Note1)
DD8(Note1)
DD10(Note1)
DD12(Note1)
DD15(Note1)
DD13(Note1)
DD11(Note1)
DD9(Note1)
DD2(Note1)
DD3(Note1)
DD1(Note1)
DD4(Note1)
DD14(Note1)
-
Input
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
Input/
output
VREF0
AVCC0
AD0IN0
AD0IN1
AD0IN2
AD0IN3
AD0IN4
AD0IN5
AD0IN6
AD0IN7
AD0IN8
AD0IN9
AD0IN10
AD0IN11
AD0IN12
AD0IN13
AD0IN14
AD0IN15
DB2
DB5
DB6
DB7
DB8
DB10
DB12
DB14
DB15
DB13
DB11
DB9
DB1
DB3
DB4
Port
-
P02
P05
P06
P11
P10
P13
P12
P15
P14
P16
P17
P01
P03
P04
P07
Function 1
Function 2
Function
Type
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
During single-chip and
external extension modes
During processor mode
VREF0
AVCC0
AD0IN0
AD0IN1
AD0IN2
AD0IN3
AD0IN4
AD0IN5
AD0IN6
AD0IN7
AD0IN8
AD0IN9
AD0IN10
AD0IN11
AD0IN12
AD0IN13
AD0IN14
AD0IN15
-
Input
-
Hi-Z
-
Hi-Z
P01
Input
Hi-Z
DB1
Input/output
Hi-Z
P02
Input
Hi-Z
DB2
Input/output
Hi-Z
P03
Input
Hi-Z
DB3
Input/output
Hi-Z
P04
Input
Hi-Z
DB4
Input/output
Hi-Z
P05
Input
Hi-Z
DB5
Input/output
Hi-Z
P06
Input
Hi-Z
DB6
Input/output
Hi-Z
P07
Input
Hi-Z
DB7
Input/output
Hi-Z
P10
Input
Hi-Z
DB8
Input/output
Hi-Z
P11
Input
Hi-Z
DB9
Input/output
Hi-Z
P12
Input
Hi-Z
DB10
Input/output
Hi-Z
P13
Input
Hi-Z
DB11
Input/output
Hi-Z
P14
Input
Hi-Z
DB12
Input/output
Hi-Z
P15
Input
Hi-Z
DB13
Input/output
Hi-Z
P16
Input
Hi-Z
DB14
Input/output
Hi-Z
P17
Input
Hi-Z
DB15
Input/output
Hi-Z
Condition
1.4 Pin Assignments