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型號：	M32185F4VFP
元件分類：	微控制器/微處理器
英文描述：	32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
封裝：	20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù)：	470/1032頁
文件大?。?/td>	5750K
代理商：	M32185F4VFP

10.8 TOU (Output-Related 24-Bit Timer)

MULTIJUNCTION TIMERS

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Note: If theare are CPU, DMA, SDI, Writing cycle from NBD to any other area between 1 and 2,

the continuous setting ( A pair of two consecutive is 1 set for writing operation) is disabled

and the writing value is not reflected. Therefore, disable interrupts and DMA transfers

before setting. However the writing cycle from RTD and DRI are not effected.

(2) Using the PWM Output Disable Control Registers to disable PWM outputs

The PWM Output 0 Disable Control Gm Register (PO0DISGACR, PO0DISGBCR) may be used to disable

outputs from the ports P87(P00)/TO21–P82(P05)/TO26 that are provided for the PWM outputs of the timer

TOU0_0–TOU0_5. Similarly, the PWM Output 1 Disable Control Gm Register (PO1DISGACR,

PO1DISGBCR) may be used to disable outputs from the ports P110(P10)/TO29–P115(P15)/TO34 that are

provided for the PWM outputs of the timer TOU1_0–TOU1_5.

To disable PWM Output by the PWM Output Disable Control Gm Register (POnDISGACR, POnDISCBCR)

set as described below.

When using the PWM Output 0 Disable Control Register (PO0DISGACR, PO0DISGBCR) to disable

PWM outputs

1. Set the PO0DISGACR(PO0DISGBCR) register PO0DISGAP(PO0DISGBP) bit to “1.”

2. After 1 above, set the PO0DISGAP(PO0DISGBP) bit to “0” and then the PO0DISGA(PO0DISGB) bit

to “1” (output disabled).

Note: If there are writing cycles to other areas between 1 and 2, setting to PO0DISGA

(PO0DISGB) bit is invalid.

When using the PWM Output 1 Disable Control Register (PO1DISGACR, PO1DISGBCR) to disable

PWM outputs

1. Set the PO1DISGACR(PO1DISGBCR) register PO1DISGAP(PO1DISGBP) bit to “1.”

2. After 1 above, set the PO1DISGAP(PO1DISGBP) bit to “0” and then the PO1DISGA(PO1DISGB) bit

to “1” (output disabled).

Note: If there are writing cycles to other areas between 1 and 2, setting to PO0DISGA

(PO0DISGB) bit is invalid.

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