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10.4 TIO (Input/Output-Related 16-Bit Timer)
MULTIJUNCTION TIMERS
10
10-121
32185/32186 Group Hardware Manual
Rev.1.10 REJ09B0235-0110 May 15, 07
10.4.14 Operation in TIO Continuous Output Mode (without Correction Function)
(1) Outline of TIO continuous output mode
In continuous output mode, the timer counts down starting from the set value of the counter and the next
cycle when the counter underflows, it is loaded with the value that " the reload 0 register -1." Thereafter, this
operation is repeated each time the counter underflows, thus generating consecutive pulses whose wave-
form is inverted in width of " reload 0 register set value + 1."
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the
counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the
count clock and when the minimum count is reached, generates an underflow. The cycle after this under-
flow causes the counter to be loaded with the content of " the reload 0 register -1" and start counting over
again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable
count by writing to the enable bit in software. The timing for reloading to counter is the cycle after underflow.
The F/F output waveform in continuous output mode is inverted (F/F output level changes from "L" to "H" or
vice versa) at startup and upon underflow, generating a waveform of consecutive pulses until the timer
stops counting.
Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TIO8
and TIO9) each time the counter underflows.
The " counter set value + 1" and " reload 0 register set value + 1" are effective as count values. (For counting
operation, see also Section 10.3.11, “Operation of TOP Continuous Output Mode.”)
(2) Precautions about using TIO continuous output mode
The following describes precautions to be observed when using TIO continuous output mode.
If the timer is enabled by external input in the same clock period as count is disabled by writing to the
enable bit, the latter has priority so that count is disabled.
If the counter is accessed for read at the cycle of underflow, the counter value is read out as H’FFFF but
changes to "reload register value -1" at the next count clock timing.
Because the timer operates synchronously with the count clock, up to one count clock-dependent delay
is generated before F/F output is inverted after writing to the enable bit.