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型號(hào)：	M32185F4VFP
元件分類：	微控制器/微處理器
英文描述：	32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
封裝：	20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁(yè)數(shù)：	181/1032頁(yè)
文件大?。?/td>	5750K
代理商：	M32185F4VFP

INPUT/OUTPUT PORTS AND PIN FUNCTIONS

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

8.3.4 Port Input Special Function Control Register

Port Input Special Function Control Register (PICNT)

<Address: H’0080 0745>

No function assigned. Fix to "0."

0: XIN oscillating

XIN oscillation status bit

1: XIN inactive

No function assigned. Fix to "0."

0: Content of port output latch

Port input data select bit

1: Port pin level

0: Disable input

Port input enable bit (Note 2)

1: Enable input

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.

Note 2: After switching from output mode to input mode in the Port Direction Register, or after setting port input enable (PIEN0) bit to

"1" (input enable), pin level can be read after 2BCLK period.

(1) XSTAT (XIN oscillation status) bit (Bit 11)

Conditions under which XSTAT bit is set to "1"

XSTAT bit is set to "1" upon detecting that XIN oscillation has stopped. When XIN remains at the same level for

a predetermined time (3 BCLK periods up to 4 BCLK periods) on the basis of threshold, XIN oscillation is as-

sumed to have stopped. When operating normally, XIN changes state ("H" or "L") once every BCLK period.

Conditions under which XSTAT bit is cleared to "0"

XSTAT bit is cleared to "0" by a system reset or by writing "0." If XSTAT bit is cleared at the same time it is

set XSTAT to "1" in above mentioned, the former has priority. Writing "1" to XSTAT bit is ignored.

Method for using XSTAT bit to detect XIN oscillation stoppage

Because the M32R/ECU internally contains a PLL, the internal clock remains active even when XIN

oscillation has stopped.

By reading XSTAT bit without clearing it once after exiting the reset state, it is possible to know whether

XIN has ever stopped since the reset signal was deasserted. Similarly, by reading XSTAT after clearing it

by writing "0," it is possible to know the current oscillating status of XIN. However, there must be an

interval of at least 5 BCLK periods (20 CPU clock periods) between read and write.

Pay attention about processing when XSTAT bit is set to "1," make double check after clearing XSTAT bit etc.

8.3 Input/Output Port Related Registers

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