參數(shù)資料
型號(hào): LPC47U33x
廠商: SMSC Corporation
英文描述: 100 Pin Enhanced Super I/O for LPC Bus with Consumer Features and SMBus Controller
中文描述: 100引腳增強(qiáng)的超級(jí)I / LPC總線為O與消費(fèi)特點(diǎn)和SMBus控制器
文件頁(yè)數(shù): 140/252頁(yè)
文件大小: 1000K
代理商: LPC47U33X
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140
Either Edge Triggered Interrupts
Six GPIO pins are implemented such that they
allow an interrupt (PME or SMI) to be generated
on both a high-to-low and a low-to-high edge
transition, instead of one or the other as
selected by the polarity bit.
The either edge triggered interrupts (EETI)
function as follows: If the EETI function is
selected for the GPIO pin, then the bits that
control
input/output,
collector/push-pull have no effect on the function
of the pin. However, the polarity bit does affect
the value of the GP bit (i.e., register GP2, bit 2
for GP22).
polarity
and
open
Either edge transition on the GPIO pin can
cause a PME or SMI interrupt if the PME or SMI
enable bit is set for the corresponding GPIO and
the EETI function is selected on the GPIO. The
PME or SMI status bits are set when the EETI
pin transitions (on either edge) and are cleared
on a write of ‘1’. There are also status bits for
the EETIs located in the MSC_STS register,
which are also cleared on a write of ‘1’. The
MSC_STS register provides the status of all of
the EETI interrupts within one register. The
PME, SMI or MSC status is valid whether or not
the interrupt is enabled and whether or not the
EETI function is selected for the pin.
The Miscellaneous Status Register (MSC_STS)
contains the either edge triggered interrupt
status bits. If the EETI function is selected for a
GPIO then both a high-to-low and a low-to-high
edge will set the corresponding MSC status bits.
Status bits are cleared on a write of ‘1’. See
Runtime Register section for more information.
LED Functionality
The LPC47U33x provides LED functionality on
two GPIOs, GP60 and GP61. These pins can be
configured to turn the LED on and off and blink
independent of each other through the LED1
and LED2 runtime registers at offset 0x5D and
0x5E from the base address located in the
primary base I/O address in Logical Device A.
The LED pins (GP60 and GP61) are able to
control the LED while the part is under VTR
power with VCC removed. In order to control a
LED while the part is under VTR power, the
GPIO pin must be configured for the LED
function and either open drain or push-pull
buffer type. In the case of open-drain buffer
type, the pin is capable of sinking current to
control the LED. In the case of push-pull buffer
type, the part will source current. The part is
also able to blink the LED under VTR power.
The LED will not blink under VTR power (VCC
removed) if the external 32kHz clock is not
connected.
The LED pins can drive a LED when the buffer
type is configured to be push-pull and the part is
powered by either VCC or VTR, since the
buffers for these pins are powered by VTR. This
means they will source their specified current
from VTR even when VCC is present.
The LED control registers are defined in the
“Runtime Register” section.
Watch Dog Timer
The LPC47U33x contains a Watch Dog Timer
(WDT). The Watch Dog Time-out status bit may
be mapped to an interrupt through the
WDT_CFG Runtime Register.
The LPC47U33x's WDT has a programmable
time-out ranging from 1 to 255 minutes with one
minute resolution, or 1 to 255 seconds with 1
second resolution. The units of the WDT
timeout value are selected via bit[7] of the
WDT_TIMEOUT register (Runtime register at
offset 0x52h). The WDT time-out value is set
through the WDT_VAL Runtime register.
Setting the WDT_VAL register to 0x00 disables
the WDT function (this is its power on default).
Setting the WDT_VAL to any other non-zero
value will cause the WDT to reload and begin
counting down from the value loaded. When the
WDT count value reaches zero the counter
stops and sets the Watchdog time-out status bit
in the WDT_CTRL Runtime Register. Note:
Regardless of the current state of the WDT, the
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