參數(shù)資料
型號(hào): ISP1583BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64
文件頁數(shù): 9/87頁
文件大?。?/td> 420K
代理商: ISP1583BS
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
9 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
AD6
30
I/O
bit 6 of multiplexed address and data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
[6]
bit 7 of multiplexed address and data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
[6]
voltage regulator output (1.8 V
±
0.15 V); tapped out voltage
from the internal regulator; this regulated voltage cannot drive
external devices; decouple this pin using a 0.1
μ
F capacitor;
see
Section 8.15
not connected
mode selection input 1; used in split bus mode only:
LOW: ALE function (address latch enable)
HIGH: A0 function (address/data indicator).
Remark:
When operating in generic processor mode, set pin
MODE1 HIGH.
input pad; TTL; 5 V tolerant
[6]
digital ground
Address latch enable input —
When pin MODE1 = LOW
during power-up, a falling edge latches the address on the
multiplexed address and data bus AD[7:0].
AD7
31
I/O
V
CC(1V8)
[3]
32
-
n.c.
MODE1
33
34
-
I
DGND
ALE/A0
35
36
-
I
Address and data selection input —
When pin
MODE1 = HIGH during power-up, the function is determined
by the level on this pin (detected on the rising edge of the
WR_N pulse):
HIGH: bus AD[7:0] is a register address
LOW: bus AD[7:0] is register data; used in split bus mode
only.
Remark:
When operating in generic processor mode with pin
MODE1 = HIGH, this pin must be pulled down using a 10 k
resistor.
input pad; TTL; 5 V tolerant
[6]
bit 0 of bidirectional data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
[6]
bit 1 of bidirectional data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
[6]
bit 2 of bidirectional data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
[6]
bit 3 of bidirectional data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
[6]
I/O pad supply voltage (1.65 V to 3.6 V); see
Section 8.15
bit 4 of bidirectional data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
[6]
bit 5 of bidirectional data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
[6]
DATA0
37
I/O
DATA1
38
I/O
DATA2
39
I/O
DATA3
40
I/O
V
CC(I/O)
[3]
DATA4
41
42
-
I/O
DATA5
43
I/O
Table 2:
Symbol
[1]
Pin description
…continued
Pin
Type
[2]
Description
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