參數(shù)資料
型號(hào): ISP1583BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64
文件頁(yè)數(shù): 37/87頁(yè)
文件大?。?/td> 420K
代理商: ISP1583BS
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
37 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.3.2
Control Function register (address: 28h)
The Control Function register performs the buffer management on endpoints. It
consists of 1 byte, and the bit configuration is given in
Table 34
. The register bits can
stall, clear or validate any enabled data endpoint. Before accessing this register, the
Endpoint Index register must be written first to specify the target endpoint.
Table 31:
Bit
Symbol
Reset
Bus reset
Access
Endpoint Index register: bit allocation
7
reserved
-
-
R/W
6
5
4
3
2
1
0
EP0SETUP
0
0
R/W
ENDPIDX[3:0]
0
0
R/W
DIR
0
0
R/W
-
-
0
0
0
0
0
0
R/W
R/W
R/W
R/W
Table 32:
Bit
7 to 6
5
Endpoint Index register: bit description
Symbol
Description
-
reserved
EP0SETUP
Selects the SETUP buffer for endpoint 0.
0 —
EP0 data buffer
1 —
SETUP buffer.
Must be logic 0 for access to other endpoints than endpoint 0.
ENDPIDX[3:0]
Endpoint Index:
Selects the target endpoint for register access
of Buffer Length, Control Function, Data Port, Endpoint Type
and MaxPacketSize.
DIR
Direction bit:
Sets the target endpoint as IN or OUT.
4 to 1
0
0 —
target endpoint refers to OUT (RX) FIFO
1 —
target endpoint refers to IN (TX) FIFO.
Table 33:
Buffer name
SETUP
Data OUT
Data IN
Addressing of endpoint 0 buffers
EP0SETUP
1
0
0
ENDPIDX
00h
00h
00h
DIR
0
0
1
Table 34:
Bit
Symbol
Reset
Bus reset
Access
Control Function register: bit allocation
7
reserved
-
-
R/W
R/W
6
5
4
3
2
1
0
CLBUF
0
0
R/W
VENDP
0
0
R/W
DSEN
0
0
R/W
STATUS
0
0
R/W
STALL
0
0
R/W
-
-
-
-
R/W
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