參數(shù)資料
型號: ISP1583BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64
文件頁數(shù): 59/87頁
文件大小: 420K
代理商: ISP1583BS
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
59 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.5.2
Chip ID register (address: 70h)
This read-only register contains the chip identification and the hardware version
numbers. The firmware should check this information to determine the functions and
features supported. The register contains 3 bytes, and the bit allocation is shown in
Table 83
.
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
EP5RX
EP4TX
EP4RX
EP3TX
EP3RX
EP2TX
EP2RX
EP1TX
EP1RX
EP0TX
EP0RX
-
EP0SETUP
VBUS
DMA
HS_STAT
logic 1 indicates the endpoint 5 RX buffer as interrupt source.
logic 1 indicates the endpoint 4 TX buffer as interrupt source.
logic 1 indicates the endpoint 4 RX buffer as interrupt source.
logic 1 indicates the endpoint 3 TX buffer as interrupt source.
logic 1 indicates the endpoint 3 RX buffer as interrupt source.
logic 1 indicates the endpoint 2 TX buffer as interrupt source.
logic 1 indicates the endpoint 2 RX buffer as interrupt source.
logic 1 indicates the endpoint 1 TX buffer as interrupt source.
logic 1 indicates the endpoint 1 RX buffer as interrupt source.
logic 1 indicates the endpoint 0 data TX buffer as interrupt source.
logic 1 indicates the endpoint 0 data RX buffer as interrupt source.
reserved
logic 1 indicates that a SETUP token was received on endpoint 0.
logic 1 indicates V
BUS
is turned on.
DMA status:
Logic 1 indicates a change in the DMA Status register.
High speed status:
Logic 1 indicates a change from full-speed to
high-speed mode (HS connection). This bit is not set, when the
system goes into full-speed suspend.
Resume status:
Logic 1 indicates that a status change from
suspend to resume (active) was detected.
Suspend status:
Logic 1 indicates that a status change from active
to suspend was detected on the bus.
Pseudo SOF interrupt:
Logic 1 indicates that a pseudo SOF or
μ
SOF was received. Pseudo SOF is an internally generated clock
signal (full-speed: 1 ms period, high-speed: 125
μ
s period)
synchronized to the USB bus SOF or
μ
SOF.
SOF interrupt:
Logic 1 indicates that a SOF or
μ
SOF was received.
Bus reset
: Logic 1 indicates that a USB bus reset was detected.
When bit OTG in the OTG register is set, BRESET will not be set,
instead, this interrupt bit will report SE0 on DP and DM for 2 ms.
4
RESUME
3
SUSP
2
PSOF
1
0
SOF
BRESET
Table 82:
Bit
Interrupt register: bit description
…continued
Symbol
Description
Table 83:
Bit
Symbol
Reset
Bus reset
Access
Chip ID register: bit allocation
23
22
21
20
19
18
17
16
CHIPID[15:8]
1
1
R
0
0
R
0
0
R
0
0
R
0
0
R
1
1
R
0
0
R
1
1
R
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