參數(shù)資料
型號: ISP1583BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64
文件頁數(shù): 38/87頁
文件大?。?/td> 420K
代理商: ISP1583BS
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
38 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.3.3
Data Port register (address: 20h)
This 2-byte register provides direct access for a microcontroller to the FIFO of the
indexed endpoint. The bit allocation is shown in
Table 36
.
Peripheral-to-host (IN endpoint):
After each write action, an internal counter is auto
incremented (by two for a 16-bit access, by one for an 8-bit access) to the next
location in the TX FIFO. When all bytes have been written (FIFO byte
count = endpoint MaxPacketSize), the buffer is automatically validated. The data
packet will then be sent on the next IN token. When it is necessary to validate the
endpoint whose byte count is less than MaxPacketSize, it can be done using the
Control Function register (bit VENDP).
Host-to-peripheral (OUT endpoint)
: After each read action, an internal counter is
auto decremented (by two for a 16-bit access, by one for an 8-bit access) to the next
location in the RX FIFO. When all bytes have been read, the buffer contents are
automatically cleared. A new data packet can then be received on the next OUT
token. The buffer contents can also be cleared through the Control Function register
(bit CLBUF), when it is necessary to forcefully clear the contents.
Table 35:
Bit
7 to 5 -
4
Control Function register: bit description
Symbol Description
reserved.
CLBUF
Clear Buffer:
Logic 1 clears the RX buffer of the indexed endpoint; the TX
buffer is not affected. The RX buffer is automatically cleared once the
endpoint is completely read. This bit is set only when it is necessary to
forcefully clear the buffer.
VENDP
Validate Endpoint:
Logic 1 validates the data in the TX FIFO of an IN
endpoint for sending on the next IN token. In general, the endpoint is
automatically validated when its FIFO byte count has reached the endpoint
MaxPacketSize. This bit is set only when it is necessary to validate the
endpoint with the FIFO byte count which is below the Endpoint
MaxPacketSize.
DSEN
Data Stage Enable
: This bit controls the response of the ISP1583 to a
control transfer. When this bit is set, the ISP1583 goes to the data stage;
otherwise, the ISP1583 will NAK the data stage transfer until the firmware
explicitly responds to the setup command.
STATUS
Status Acknowledge:
Only applicable for control IN/OUT.
This bit controls the generation of ACK or NAK during the status stage of a
SETUP transfer. It is automatically cleared when the status stage is
completed, or when a SETUP token is received. No interrupt signal will be
generated.
3
2
1
0 —
Sends NAK
1 —
Sends an empty packet following the IN token (host-to-peripheral) or
ACK following the OUT token (peripheral-to-host).
Stall Endpoint
: Logic 1 stalls the indexed endpoint. This bit is not
applicable for isochronous transfers.
Remark:
‘Stall’ing a data endpoint will confuse the Data Toggle bit about
the stalled endpoint because the internal logic picks up from where it is
stalled. Therefore, the Data Toggle bit must be reset by disabling and
re-enabling the corresponding endpoint (by setting bit ENABLE to logic 0 or
logic 1 in the Endpoint Type register) to reset the PID.
0
STALL
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