參數(shù)資料
型號(hào): ISP1583BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64
文件頁(yè)數(shù): 11/87頁(yè)
文件大小: 420K
代理商: ISP1583BS
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
11 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
[2]
[3]
Symbol names ending with underscore N (for example, NAME_N) represent active LOW signals.
All outputs and I/O pins can source 4 mA.
Add a decoupling capacitor (0.1
μ
F) to all the supply pins. For better EMI results, add a 0.01
μ
F
capacitor in parallel to the 0.1
μ
F.
The DMA bus is in 3-state until a DMA command (see
Section 9.4.1
) is executed.
The control signals are not 3-state.
5 V tolerant when V
CC(I/O)
= 3.3 V.
[4]
[5]
[6]
MODE0/
DA1
[5]
60
I/O
Mode selection input 0 —
Selects the read/write strobe
functionality in generic processor mode during power-up:
LOW: for Motorola style; the function of pin 19 is RW_N and
pin 20 is DS_N
HIGH: for 8051 style; the function of pin 19 is RD_N and
pin 20 is WR_N.
Address selection output —
Selects the Task File register of
an ATA/ATAPI device during normal operation; see
Table 59
bidirectional pad; 10 ns slew-rate control; TTL; 5 V tolerant
[6]
regulator supply voltage (3.3 V
±
0.3 V); this pin supplies the
internal regulator; see
Section 8.15
Bus configuration input —
Selects bus mode during
power-up at:
LOW: split bus mode; multiplexed 8-bit address and data
bus on AD[7:0], separate DMA data bus on DATA[15:0]
[4]
HIGH: generic processor mode; separate 8-bit address on
AD[7:0], 16-bit processor data bus on DATA[15:0]. DMA is
multiplexed on the processor bus as DATA[15:0].
V
CC(3V3)
[3]
61
-
BUS_CONF/
DA0
[5]
62
I/O
Address selection output —
Selects the Task File register of
an ATA/ATAPI device at normal operation; see
Table 59
bidirectional pad; 10 ns slew-rate control; TTL; 5 V tolerant
[6]
wake-up input; when this pin is at the HIGH level, the chip is
prevented from getting into the suspend state and the chip
wakes up from the suspend state; when not in use, connect
this pin to ground through a 10 k
resistor
input pad; TTL; 5 V tolerant
[6]
suspend state indicator output; used as a power switch control
output for powered-off application or as a resume signal to the
CPU for powered-on application
CMOS output; 8 mA drive
ground supply; down bonded to the exposed die pad
(heatsink); to be connected to the DGND during PCB layout
WAKEUP
63
I
SUSPEND
64
O
GND
exposed die
pad
Table 2:
Symbol
[1]
Pin description
…continued
Pin
Type
[2]
Description
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