參數(shù)資料
型號: ISP1583BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64
文件頁數(shù): 48/87頁
文件大?。?/td> 420K
代理商: ISP1583BS
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
48 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Bit
Symbol
7
6
5
4
3
2
1
0
DIS_
XFER_CNT
0
0
R/W
reserved
MODE[1:0]
reserved
WIDTH
Reset
Bus Reset
Access
0
0
0
0
0
0
0
0
0
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 55:
Bit
15 to 14 -
13
DMA Configuration register: bit description
[1]
Symbol
Description
reserved
ATA_MODE
Mode selection of the DMA core.
0 —
Configures the DMA core for ATA or MDMA mode. Used
when issuing DMA commands 02h to 07h, 0Ah and 0Ch; also
used when directly accessing Task File registers.
1 —
Configures the DMA core for non-ATA mode. Used when
issuing DMA commands 00h and 01h.
Logic 1 configures the DMA core for ATA or MDMA mode.
Used when issuing DMA commands 02h to 07h, 0Ah and
0Ch; also used when directly accessing Task File registers.
Logic 0 configures the DMA core for non-ATA mode. Used
when issuing DMA commands 00h and 01h.
These bits affect the timing for MDMA mode.
13
ATA_MODE
12 to 11 DMA_MODE[1:0]
00 —
MDMA mode 0: ATA(PI) compatible timings
01 —
MDMA mode 1: ATA(PI) compatible timings
10 —
MDMA mode 2: ATA(PI) compatible timings
11 —
MDMA mode 3: enables the DMA Strobe Timing
register (see
Table 77
and
Table 78
) for non-standard strobe
durations; only used in MDMA mode.
These bits affect the PIO timing.
10 to 8
PIO_MODE[2:0]
[2]
000 to 100 —
PIO mode 0 to 4: ATA(PI) compatible timings
101 to 111 —
reserved.
Logic 1 disables the DMA Transfer Counter (see
Table 52
).
The transfer counter can be disabled only in GDMA slave
mode; in master mode the counter is always enabled.
reserved
7
DIS_XFER_CNT
6 to 4
-
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