參數(shù)資料
型號(hào): ISP1583BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64
文件頁(yè)數(shù): 20/87頁(yè)
文件大?。?/td> 420K
代理商: ISP1583BS
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
20 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.14 Power-on reset
The ISP1583 requires a minimum pulse width of 500
μ
s.
The RESET_N pin can be either connected to V
CC(3V3)
(using the internal POR
circuit) or externally controlled (by the microcontroller, ASIC, and so on). When
V
CC(3V3)
is directly connected to the RESET_N pin, the internal pulse width t
PORP
will
be typically 200 ns.
The power-on reset function can be explained by viewing the dips at t2-t3 and t4-t5
on the V
CC(POR)
curve (
Figure 9
).
t0 —
The internal POR starts with a HIGH level.
t1 —
The detector will see the passing of the trip level and a delay element will add
another t
PORP
before it drops to LOW.
t2-t3 —
The internal POR pulse will be generated whenever V
CC(POR)
drops below
V
trip
for more than 11
μ
s.
t4-t5 —
The dip is too short (< 11
μ
s) and the internal POR pulse will not react and
will remain LOW.
Figure 10
shows the availability of the clock with respect to the external POR.
8.15 Power supply
The ISP1583 can be powered by 3.3 V
±
0.3 V, and from 1.65 V to 3.6 V at the
interface. For connection details, see
Figure 11
.
(1) PORP = power-on reset pulse.
Fig 9.
POR timing.
Stable external clock is to be available at A.
Fig 10. Clock with respect to the external POR.
004aaa389
VBAT(POR)
t0
t1
t2
t3
t4
t5
Vtrip
tPORP
PORP(1)
tPORP
POR
EXTERNAL CLOCK
A
004aaa365
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