參數(shù)資料
型號: ISP1583BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64
文件頁數(shù): 79/87頁
文件大小: 420K
代理商: ISP1583BS
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
79 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
13.2.3
MDMA mode
[1]
T
cy1
is the total cycle time, consisting of command active time t
w1
and command recovery (inactive) time t
w2
, that is, T
cy1
= t
w1
+ t
w2
. The
minimum timing requirements for T
cy1
, t
w1
and t
w2
must all be met. As T
cy1(min)
is greater than the sum of t
w1(min)
and t
w2(min)
, a host
implementation must lengthen t
w1
and/or t
w2
to ensure that T
cy1
is equal to or greater than the value reported in the IDENTIFY DEVICE
data. A device implementation shall support any legal host implementation.
Table 106: MDMA mode timing parameters
V
CC(I/O)
= 3.3 V; V
CC(3V3)
= 3.3 V; V
GND
= 0 V; T
amb
=
40
°
C to +85
°
C.
Symbol
Parameter
T
cy1(min)
read/write cycle time
t
w1(min)
DIOR/DIOW pulse width
t
d1(max)
data valid delay after DIOR on
t
h3(min)
data hold time after DIOR off
t
su2(min)
data set-up time before DIOR/DIOW off
t
h2(min)
data hold time after DIOW off
t
su1(min)
DACK set-up time before DIOR/DIOW on
t
h1(min)
DACK hold time after DIOR/DIOW off
t
w2(min)
DIOR recovery time)
DIOW recovery time
t
d2(max)
DIOR on to DREQ off delay
DIOW on to DREQ off delay
t
d3(max)
DACK off to data lines 3-state delay
Mode 0
Mode 1
150
80
60
5
30
15
0
5
50
50
40
40
25
Mode 2
120
70
50
5
20
10
0
5
25
25
35
35
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[1]
480
[1]
215
150
5
100
20
0
20
[1]
50
[1]
215
120
40
20
(1) Programmable polarity: shown as active LOW.
(2) Programmable polarity: shown as active HIGH.
Fig 33. MDMA master mode timing.
(write) DATA[15:0]
(read) DATA[15:0]
DREQ
(2)
DACK
(1)
DIOR/DIOW
(1)
tw1
tw2
tsu1
tsu2
td2
tsu2
th1
th2
th3
Tcy1
MGT506
td1
td3
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