參數(shù)資料
型號： ISP1583BS
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Hi-Speed Universal Serial Bus peripheral controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝： 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64
文件頁數(shù)： 35/87頁
文件大?。?/td> 420K
代理商： ISP1583BS
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
35 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
An interrupt is generated when the USB SIE receives or generates an ACK or NAK
on the USB bus. The interrupt generation depends on Debug mode settings of bit
fields CDBGMOD[1:0], DDBGMODIN[1:0] and DDBGMODOUT[1:0].
All data IN transactions use the Transmit buffers (TX), which are handled by bits
DDBGMODIN. All data OUT transactions go via the Receive buffers (RX), which are
handled by bits DDBGMODOUT. Transactions on control endpoint 0 (IN, OUT and
SETUP) are handled by bits CDBGMOD.
Interrupts caused by events on the USB bus (SOF, Pseudo SOF, suspend, resume,
bus reset, setup and high-speed status) can also be individually controlled. A bus
reset disables all enabled interrupts except bit IEBRST (bus reset), which remains
unchanged.
The Interrupt Enable register consists of 4 bytes. The bit allocation is given in
Table 29
.
Table 29:
Bit
Symbol
Reset
Bus Reset
Access
Bit
Symbol
Reset
Bus Reset
Access
Bit
Symbol
Reset
Bus Reset
Access
Bit
Symbol
Reset
Bus Reset
Access
Interrupt Enable register: bit allocation
31
30
29
28
27
26
25
24
reserved
IEP7TX
0
0
R/W
17
IEP3TX
0
0
R/W
9
reserved
-
-
R/W
1
IESOF
0
0
R/W
IEP7RX
0
0
R/W
16
IEP3RX
0
0
R/W
8
IEP0SETUP
0
0
R/W
0
IEBRST
0
unchanged
R/W
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23
22
21
20
19
18
IEP6TX
0
0
R/W
15
IEP2TX
0
0
R/W
7
IEVBUS
0
0
R/W
IEP6RX
0
0
R/W
14
IEP2RX
0
0
R/W
6
IEDMA
0
0
R/W
IEP5TX
0
0
R/W
13
IEP1TX
0
0
R/W
5
IEHS_STA
0
0
R/W
IEP5RX
0
0
R/W
12
IEP1RX
0
0
R/W
4
IERESM
0
0
R/W
IEP4TX
0
0
R/W
11
IEP0TX
0
0
R/W
3
IESUSP
0
0
R/W
IEP4RX
0
0
R/W
10
IEP0RX
0
0
R/W
2
IEPSOF
0
0
R/W
Table 30:
Bit
31 to 26
25
24
23
22
21
Interrupt Enable register: bit description
Symbol
Description
-
reserved
IEP7TX
Logic 1 enables interrupt from the indicated endpoint.
IEP7RX
Logic 1 enables interrupt from the indicated endpoint.
IEP6TX
Logic 1 enables interrupt from the indicated endpoint.
IEP6RX
Logic 1 enables interrupt from the indicated endpoint.
IEP5TX
Logic 1 enables interrupt from the indicated endpoint.
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