參數(shù)資料
型號(hào): ISP1583BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64
文件頁(yè)數(shù): 8/87頁(yè)
文件大?。?/td> 420K
代理商: ISP1583BS
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
8 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
READY/
IORDY
15
I/O
Signal ready output —
Used in generic processor mode:
LOW: the ISP1583 is processing a previous command or
data and is not ready for the next command or data transfer
HIGH: the ISP1583 is ready for the next microprocessor
read or write.
DMA ready input —
Used in split bus mode for accessing
ATA/ATAPI peripherals (PIO mode only).
bidirectional pad; 10 ns slew-rate control; TTL; 5 V tolerant
[6]
interrupt output; programmable polarity (active HIGH or LOW)
and signaling (edge or level triggered)
CMOS output; 8 mA drive
address output to select the Task File register of an ATA/ATAPI
device; see
Table 59
CMOS output; 8 mA drive
chip selection input
input pad; TTL; 5 V tolerant
[6]
Read and write input —
For Motorola style, this function is
determined by pin MODE0 = LOW during power-up.
INT
16
O
DA2
[5]
17
O
CS_N
18
I
RW_N/
RD_N
19
I
Read input —
For 8051 style, this function is determined by
pin MODE0 = HIGH during power-up.
input pad; TTL; 5 V tolerant
[6]
Data selection input —
For Motorola style, this function is
determined by pin MODE0 = LOW at power-up.
DS_N/
WR_N
20
I
Write input —
For 8051 style, this function is determined by
pin MODE0 = HIGH at power-up.
input pad; TTL; 5 V tolerant
[6]
chip selection output 0 for ATA/ATAPI device; see
Table 59
CMOS output; 8 mA drive
chip selection output 1 for ATA/ATAPI device; see
Table 59
CMOS output; 8 mA drive
bit 0 of multiplexed address and data
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
[6]
bit 1 of multiplexed address and data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
[6]
bit 2 of multiplexed address and data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
[6]
I/O pad supply voltage (1.65 V to 3.6 V); see
Section 8.15
bit 3 of multiplexed address and data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
[6]
bit 4 of multiplexed address and data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
[6]
bit 5 of multiplexed address and data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
[6]
CS0_N
[5]
21
O
CS1_N
[5]
22
O
AD0
23
I/O
AD1
24
I/O
AD2
25
I/O
V
CC(I/O)
[3]
AD3
26
27
-
I/O
AD4
28
I/O
AD5
29
I/O
Table 2:
Symbol
[1]
Pin description
…continued
Pin
Type
[2]
Description
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