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參數資料
| 型號： | ISP1583BS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Hi-Speed Universal Serial Bus peripheral controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQCC64 |
| 封裝： | 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64 |
| 文件頁數： | 17/87頁 |
| 文件大小： | 420K |
| 代理商： | ISP1583BS |
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Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
17 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
pin INT; see
Table 22
. Default settings after reset are active LOW and level mode.
When pulse mode is selected, a pulse of 60 ns is generated when the OR-ed
combination of all interrupt bits changes from logic 0 to logic 1.
Figure 4
shows the relationship between the interrupt events and pin INT.
Each of the indicated USB and DMA events is logged in a status bit of the Interrupt
register and the DMA Interrupt Reason register, respectively. Corresponding bits in
the Interrupt Enable register and the DMA Interrupt Enable register determine
whether or not an event will generate an interrupt.
Interrupts can be masked globally by means of bit GLINTENA of the Mode register.
Field CDBGMOD[1:0] of the Interrupt Configuration register controls the generation
of the INT signals for the control pipe. Field DDBGMODIN[1:0] of the Interrupt
Configuration register controls the generation of the INT signals for the IN pipe. Field
DDBGMODOUT[1:0] of the Interrupt Configuration register controls the generation of
the INT signals for the OUT pipe; see
Table 26
.
8.12.2
Interrupt control
Bit GLINTENA in the Mode register is a global enable/disable bit. The behavior of this
bit is given in
Figure 5
.
Event A: When an interrupt event occurs (for example, SOF interrupt) with
bit GLINTENA set to logic 0, an interrupt will not be generated at pin INT. It will,
however, be registered in the corresponding Interrupt register bit.
Event B: When bit GLINTENA is set to logic 1, pin INT is asserted because bit SOF in
the Interrupt register is already set.
Event C: If the firmware sets bit GLINTENA to logic 0, pin INT will still be asserted.
The bold dashed line shows the desired behavior of pin INT.
Deassertion of pin INT can be achieved either by clearing all the Interrupt register or
the DMA Interrupt Reason register, depending on the event.
Remark:
When clearing an interrupt event, perform write to all the bytes of the
register.
For more information on interrupt control, see
Section 9.2.2
,
Section 9.2.5
and
Section 9.5.1
.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1583BS,518 | 功能描述:USB 接口集成電路 USB PERIPH CNTRLR RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1583BS,551 | 功能描述:USB 接口集成電路 HI-SPEED USB2 DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1583BS,557 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1583BS518 | 制造商:ST-Ericsson 功能描述:CONTROLLER USB PERIPHERAL 64HVQFN |
| ISP1583BSGA | 功能描述:IC USB CTRL HI-SPEED 64HVQFN RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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