參數(shù)資料
型號: ISP1583BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64
文件頁數(shù): 46/87頁
文件大?。?/td> 420K
代理商: ISP1583BS
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
46 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.4.2
DMA Transfer Counter register (address: 34h)
This 4-byte register sets up the total byte count for a DMA transfer (DMACR). It
indicates the remaining number of bytes left for transfer. The bit allocation is given in
Table 52
.
For IN endpoint —
As there is a FIFO in the ISP1583 DMA controller, some data
may remain in the FIFO during the DMA transfer. The maximum FIFO size is 8 bytes,
and the maximum delay time for the data to be shifted to endpoint buffer is 60 ns.
0Fh
Clear Buffer
Clear Buffer:
Request from the microcontroller to clear the
endpoint buffer after a USB-to-ATA data transfer.
Restart:
Request from the microcontroller to move the buffer
pointers to the beginning of the endpoint FIFO.
Reset DMA:
Initializes the DMA core to its power-on reset
state.
Remark:
When the DMA core is reset during the Reset DMA
command, the DREQ, DACK, DIOW and DIOR handshake
pins will be temporarily asserted. This can confuse the
external DMA Controller. To prevent this, start the external
DMA Controller
only after
the DMA reset.
MDMA stop:
This command immediately stops the MDMA
data transfer. This is applicable for commands 06h and 07h
only.
GDMA stop
: This command stops the GDMA data transfer.
Any data in the OUT endpoint that is not transferred by the
DMA will remain in the buffer. The FIFO data for the IN
endpoint will be written to the endpoint buffer. An interrupt bit
will be set to indicate the completion of the DMA Stop
command.
reserved
Read Task File register 1F1h
: When reading has been
completed, an interrupt is generated.
Read Task File register 1F2h
: When reading has been
completed, an interrupt is generated.
Read Task File register 1F3h
: When reading has been
completed, an interrupt is generated.
Read Task File register 1F4h
: When reading has been
completed, an interrupt is generated.
Read Task File register 1F5h
: When reading has been
completed, an interrupt is generated.
Read Task File register 1F6h:
. When reading has been
completed, an interrupt is generated.
Read Task File register 3F6h
: When reading has been
completed, an interrupt is generated.
Read Task File register 3F7h
: When reading has been
completed, an interrupt is generated.
reserved
10h
Restart
11h
Reset DMA
12h
MDMA stop
13h
GDMA stop
14h to 20h
21h
-
Read Task File
register 1F1h
Read Task File
register 1F2h
Read Task File
register 1F3h
Read Task File
register 1F4h
Read Task File
register 1F5h
Read Task File
register 1F6h
Read Task File
register 3F6h
Read Task File
register 3F7h
-
22h
23h
24h
25h
26h
27h
28h
29h to FFh
Table 51:
Code
DMA commands
…continued
Name
Description
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