參數(shù)資料
型號: ISP1583BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64
文件頁數(shù): 43/87頁
文件大小: 420K
代理商: ISP1583BS
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
43 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.4 DMA registers
Two types of Generic DMA transfer and three types of IDE-specified transfer can be
done by writing the proper opcode in the DMA Command register.
The control bits are given in
Table 47
(Generic DMA transfers) and
Table 48
(IDE-specified transfers).
GDMA read/write (opcode = 00h/01h) —
Generic DMA Slave mode. Depending on
the MODE[1:0] bit set in the DMA configuration register, either the DACK signal or the
DIOR/DIOW signals strobe the data. These signals are driven by the external DMA
controller.
GDMA slave mode can operate in either counter mode or EOT-only mode.
In counter mode, bit DIS_XFER_CNT in the DMA Configuration register must be set
to logic 0. The DMA Transfer Counter register must be programmed before any DMA
command is issued. The DMA transfer counter is set by writing from the LSByte to the
MSByte (address: 34h to 37h). The DMA transfer count is internally updated only
after the MSByte has been written. Once the DMA transfer is started, the transfer
counter starts decrementing and on reaching 0, bit DMA_XFER_OK is set and an
interrupt is generated by the ISP1583. If the DMA master wishes to terminate the
DMA transfer, it can issue an EOT signal to the ISP1583. This EOT signal overrides
the transfer counter and can terminate the DMA transfer at any time.
In EOT-only mode, DIS_XFER_CNT has to be set to logic 1. Although the DMA
transfer counter can still be programmed, it will not have any effect on the DMA
transfer. The DMA transfer will start once the DMA command is issued. Any of the
following three ways will terminate this DMA transfer:
Detecting an external EOT
Detecting an internal EOT (short packet on an OUT token)
Resetting the DMA.
There are three interrupts programmable to differentiate the method of DMA
termination: bits INT_EOT, EXT_EOT and DMA_XFER_OK in the DMA Interrupt
Reason register (see
Table 72
).
MDMA (master) read/write (opcode = 06h/07h) —
Generic DMA Master mode.
Depending on the MODE[1:0] bit set in the DMA Configuration register, either the
DACK signal or the DIOR/DIOW signals strobe the data. These signals are driven by
the ISP1583.
In Master mode, BURSTCOUNTER[12:0] in the DMA Burst Counter register,
DIS_XFER_CNT in the DMA Configuration register and the external EOT signal are
not applicable. The DMA transfer counter is always enabled and bit DMA_XFER_OK
is set to 1 once the counter reaches 0.
MDMA read/write (opcode = 06h/07h) —
Multiword DMA mode for IDE transfers.
The specification of this mode can be obtained from the ATA Specification Rev. 4
DIOR and DIOW are used as data strobes, while DREQ and DACK serve as
handshake signals.
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