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參數(shù)資料
| 型號： | ISP1583BS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Hi-Speed Universal Serial Bus peripheral controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQCC64 |
| 封裝： | 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64 |
| 文件頁數(shù)： | 33/87頁 |
| 文件大?。?/td> | 420K |
| 代理商： | ISP1583BS |
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Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
33 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table 27:
Bit
Symbol
Reset
Bus reset
Access
OTG register: bit allocation
7
reserved
-
-
-
6
5
4
3
2
1
0
DP
0
0
R/W
BSESSVALID
-
-
R/W
INITCOND
-
-
R/W
DISCV
0
0
R/W
VP
0
0
R/W
OTG
0
0
R/W
-
-
-
Table 28:
Bit
7 to 6
5
OTG register: bit description
[1]
Symbol
Description
-
reserved
DP
When set, data-line pulsing is started. The default value of this bit is
logic 0. This bit must be cleared when data-line pulsing is completed.
BSESSVALID
The device can initiate another V
BUS
discharge sequence after
data-line pulsing and V
BUS
pulsing, and before it clears this bit and
detects a session valid.
This bit is latched to logic 1 once V
BUS
exceeds the B-device session
valid threshold. Once set, it remains at logic 1. To clear this bit, write
logic 1. (The ISP1583 continuously updates this bit to logic 1 when
the B-session is valid. If the B-session is valid after it is cleared, it is
set back to logic 1 by the ISP1583).
4
0 —
It implies that SRP has failed. To proceed to a normal operation,
the device can restart SRP, clear bit OTG or proceed to an error
handling process.
1 —
It implies that the B-session is valid. The device clears bit OTG,
goes into normal operation mode, and sets bit SOFTCT (DP pull-up)
in the Mode register. The OTG host has a maximum of 5 s before it
responds to a session request. During this period, the ISP1583 may
request to suspend. Therefore, the device firmware must wait for
sometime if it wishes to know the SRP result (success—if there is
minimum response from the host within 5 s; failure—if there is no
response from the host within 5 s).
Write logic 1 to clear this bit. The device clears this bit, and waits for
more than 2 ms to check the bit status. If it reads logic 0, it means
that V
BUS
remains lower than 0.8 V, and DP or DM at SE0 during the
elapsed time is cleared. The device can then start a B-device SRP. If
it reads logic 1, it means that the initial condition of an SRP is
violated. So, the device should abort SRP.
The bit is set to logic 1 by the ISP1583 when initial conditions are not
met, and only writing logic 1 clears the bit. (If initial conditions are not
met after this bit has been cleared, it will be set again).
Remark:
This implementation does not cover the case if an initial
SRP condition is violated when this bit is read and data-line pulsing
is started.
3
INITCOND
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1583BS,518 | 功能描述:USB 接口集成電路 USB PERIPH CNTRLR RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1583BS,551 | 功能描述:USB 接口集成電路 HI-SPEED USB2 DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1583BS,557 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1583BS518 | 制造商:ST-Ericsson 功能描述:CONTROLLER USB PERIPHERAL 64HVQFN |
| ISP1583BSGA | 功能描述:IC USB CTRL HI-SPEED 64HVQFN RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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