參數(shù)資料
型號(hào): ISP1583BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64
文件頁數(shù): 32/87頁
文件大?。?/td> 420K
代理商: ISP1583BS
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
32 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.2.3
Interrupt Configuration register (address: 10h)
This 1-byte register determines the behavior and polarity of the INT output. The bit
allocation is shown in
Table 24
. When the USB SIE receives or generates an ACK,
NAK or STALL, it will generate interrupts depending on three Debug mode fields.
CDBGMOD[1:0] —
interrupts for the control endpoint 0
DDBGMODIN[1:0] —
interrupts for the DATA IN endpoints 1 to 7
DDBGMODOUT[1:0] —
interrupts for the DATA OUT endpoints 1 to 7.
The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow
you to individually configure when the ISP1583 sends an interrupt to the external
microprocessor.
Table 26
lists the available combinations.
Bit INTPOL controls the signal polarity of the INT output: active HIGH or LOW, rising
or falling edge. For level-triggering, bit INTLVL must be made logic 0. By setting
INTLVL to logic 1, an interrupt will generate a pulse of 60 ns (edge-triggering).
[1]
First NAK: the first NAK on an IN or OUT token after a previous ACK response.
9.2.4
OTG register (address: 12h)
The bit allocation of the OTG register is given in
Table 27
.
Table 24:
Bit
Symbol
Reset
Bus reset
Access
Interrupt Configuration register: bit allocation
7
6
CDBGMOD[1:0]
1
1
1
1
R/W
R/W
5
4
3
2
1
0
DDBGMODIN[1:0]
1
1
R/W
DDBGMODOUT[1:0]
1
1
R/W
INTLVL
0
unchanged
R/W
INTPOL
0
unchanged
R/W
1
1
1
1
R/W
R/W
Table 25:
Bit
7 to 6
5 to 4
3 to 2
1
Interrupt Configuration register: bit description
Symbol
Description
CDBGMOD[1:0]
Control 0 Debug Mode:
For values, see
Table 26
DDBGMODIN[1:0]
Data Debug Mode IN:
For values, see
Table 26
DDBGMODOUT[1:0]
Data Debug Mode OUT:
For values, see
Table 26
INTLVL
Interrupt Level
: Selects signaling mode on output INT
(0 = level; 1 = pulsed). In pulsed mode, an interrupt
produces a 60 ns pulse. Bus reset value: unchanged.
INTPOL
Interrupt Polarity:
Selects signal polarity on output INT
(0 = active LOW, 1 = active HIGH). Bus reset
value: unchanged.
0
Table 26:
Value
00h
Debug mode settings
CDBGMOD
interrupt on all ACK and
NAK
interrupt on all ACK.
interrupt on all ACK and
first NAK
[1]
DDBGMODIN
interrupt on all ACK and
NAK
interrupt on ACK
interrupt on all ACK and
first NAK
[1]
DDBGMODOUT
interrupt on all ACK, NYET
and NAK
interrupt on ACK and NYET
interrupt on all ACK, NYET
and first NAK
[1]
01h
1Xh
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