參數(shù)資料
型號(hào): ISP1583BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64
文件頁數(shù): 45/87頁
文件大?。?/td> 420K
代理商: ISP1583BS
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
45 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table 49:
Bit
Symbol
Reset
Bus reset
Access
DMA Command register: bit allocation
7
6
5
4
DMA_CMD[7:0]
1
1
W
3
2
1
0
1
1
W
1
1
W
1
1
W
1
1
W
1
1
W
1
1
W
1
1
W
Table 50:
Bit
7 to 0
DMA Command register: bit description
Symbol
Description
DMA_CMD[7:0]
DMA command code, see
Table 51
.
PIO Read or Write that started using DMA Command register
only performs a 16-bit transfer.
Table 51:
Code
00h
DMA commands
Name
GDMA Read
Description
Generic DMA IN token transfer (slave mode only):
Data is
transferred from the external DMA bus to the internal buffer.
Strobe: DIOW by external DMA Controller.
Generic DMA OUT token transfer (slave mode only):
Data
is transferred from the internal buffer to the external DMA
bus. Strobe: DIOR by external DMA Controller.
reserved
Multiword DMA Read:
Data is transferred from the external
DMA bus to the internal buffer.
Multiword DMA Write:
Data is transferred from the internal
buffer to the external DMA bus.
Read at address 1F0h:
Initiates a PIO Read cycle from Task
File 1F0. Before issuing this command, the task file byte
count should be programmed at address 1F4h (LSB) and
1F5h (MSB).
Poll BSY status bit for ATAPI device:
Starts repeated PIO
Read commands to poll the BSY status bit of the ATAPI
device. When BSY = 0, polling is terminated and an interrupt
is generated. The interrupt can be masked but the interrupt
bit will still be set. Therefore, you can manually poll this
interrupt bit.
Read Task Files
Read Task Files:
Reads all task files. When Task File Index
is set to logic 0, this command reads all registers, except
1F0h and 1F7h. If Task File Index is not logic 0, the Task
register of the address set in the Task File register will be
read. When the reading is completed, an interrupt is
generated. The interrupt could be masked off, however, the
interrupt bit will still be set. Therefore, you can manually poll
this interrupt bit.
-
reserved
Validate Buffer
Validate Buffer (for debugging only):
Request from the
microcontroller to validate the endpoint buffer following an
ATA-to-USB data transfer.
01h
GDMA Write
02h to 05h
06h
-
MDMA Read
07h
MDMA Write
0Ah
Read 1F0
0Bh
Poll BSY
0Ch
0Dh
0Eh
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