- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄67723 > ISP1362EE,551 (NXP SEMICONDUCTORS) UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 PDF資料下載
參數(shù)資料
| 型號(hào)： | ISP1362EE,551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封裝： | 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64 |
| 文件頁(yè)數(shù)： | 99/152頁(yè) |
| 文件大?。?/td> | 677K |
| 代理商： | ISP1362EE,551 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)當(dāng)前第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)
ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
50 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
12.1 Peripheral Controller data transfer operation
The following sessions explain how the Peripheral Controller in the ISP1362 handles an
IN data transfer and an OUT data transfer. An IN data transfer means transfer from the
ISP1362 to an external USB host (through the upstream port), and an OUT transfer
means transfer from an external USB host to the ISP1362. In device mode, the ISP1362
acts as a USB device.
12.1.1 IN data transfer
1. The arrival of the IN token is detected by the Serial Interface Engine (SIE) by
decoding the Packet Identier (PID).
2. The SIE also checks the device number and the endpoint number to verify whether
they are okay.
3. If the endpoint is enabled, the SIE checks the contents of the DcEndpointStatus
register (ESR). If the endpoint is full, the contents of the buffer memory are sent
during the data phase else an NAK handshake is sent.
4. After the data phase, the SIE expects a handshake (ACK) from the host (except for
ISO endpoints).
5. On receiving the handshake (ACK), the SIE updates the contents of the
DcEndpointStatus and DcInterrupt registers, which in turn generates an interrupt to
the microprocessor. For ISO endpoints, the DcInterrupt register is updated as soon as
data is sent because there is no handshake phase.
6. On receiving an interrupt, the microprocessor reads the DcInterrupt register. It knows
which endpoint has generated the interrupt and reads the contents of the
corresponding ESR. If the buffer is empty, it lls up the buffer so that data can be sent
by the SIE at the next IN token phase.
12.1.2 OUT data transfer
1. The arrival of the OUT token is detected by the SIE by decoding the PID.
2. The SIE checks the device and endpoint numbers to verify whether they are okay.
3. If the endpoint is enabled, the SIE checks the contents of the ESR. If the endpoint is
empty, the data from USB is stored in the buffer memory during the data phase else a
NAK handshake is sent.
4. After the data phase, the SIE sends a handshake (ACK) to the host (except for ISO
endpoints).
5. The SIE updates the contents of the DcEndpointStatus register and the DcInterrupt
register, which in turn generates an interrupt to the microprocessor. For ISO
endpoints, the DcInterrupt register is updated as soon as data is received because
there is no handshake phase.
6. On receiving an interrupt, the microprocessor reads the DcInterrupt register. It knows
which endpoint has generated the interrupt and reads the content of the
corresponding ESR. If the buffer is full, it empties the buffer so that data can be
received by the SIE at the next OUT token phase.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISP1520BD,557 | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| ISP1520BD,557 | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| ISP1561BM,557 | UNIVERSAL SERIAL BUS CONTROLLER, PQFP128 |
| ISP1561BM,557 | UNIVERSAL SERIAL BUS CONTROLLER, PQFP128 |
| ISP1563BM | UNIVERSAL SERIAL BUS CONTROLLER, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1362EE-S | 功能描述:IC USB CTRL SNGL CHIP 64TFBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類(lèi)型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱(chēng):Q6396337A |
| ISP1362EE-T | 功能描述:USB 接口集成電路 USB OTG HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類(lèi)型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1362EEUM | 功能描述:IC USB OTG CONTROLLER 64-TFBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類(lèi)型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱(chēng):Q6396337A |
| ISP1362PCI/DOSOTG | 制造商:NXP Semiconductors 功能描述: |
| ISP1501 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Hi-Speed Universal Serial Bus peripheral transceiver |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。