參數(shù)資料
型號: ISP1362EE,551
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù): 65/152頁
文件大?。?/td> 677K
代理商: ISP1362EE,551
ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
2 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
N Supports integrated physical 4096 bytes of multiconguration memory
N Supports all four types of USB transfers: control, bulk, interrupt and isochronous
N Supports multiframe buffering for isochronous transfer
N Supports automatic interrupt polling rate mechanism
N Supports paired buffering for bulk transfer
N Directly addressable memory architecture; memory can be updated on-the-y
I USB device:
N Supports high performance USB interface device with integrated Serial Interface
Engine (SIE), buffer memory and transceiver
N Supports fully autonomous and multiconguration Direct Memory Access (DMA)
operation
N Supports up to 14 programmable USB endpoints with two xed control IN/OUT
endpoints
N Supports integrated physical 2462 bytes of multiconguration memory
N Supports endpoints with double buffering to increase throughput and ease
real-time data transfer
N Supports controllable LazyClock (110 kHz ± 50 %) output during ‘suspend’
I Supports two USB ports: port 1 and port 2
N Port 1 can be congured to function as a downstream port, an upstream port or an
OTG port
N Port 2 can be used only as a downstream port
I Supports software-controlled connection to the USB bus (SoftConnect)
I Supports good USB connection indicator that blinks with trafc (GoodLink)
I Complies with USB power management requirements
I Supports internal power-on and low-voltage reset circuit, with possibility of a software
reset
I High-speed parallel interface to most CPUs available in the market, such as Hitachi
SH-3, Intel StrongARM, NXP XA, Fujitsu SPARClite, NEC and Toshiba MIPS, ARM7/9,
Freescale DragonBall and PowerPC Reduced Instruction Set Computer (RISC):
N 16-bit data bus
N 10 MB/s data transfer rate between the microprocessor and the ISP1362
I Supports Programmed I/O (PIO) or DMA
I Supports ‘suspend’ and remote wake-up
I Uses 12 MHz crystal or direct clock source with on-chip Phase-Locked Loop (PLL) for
low ElectroMagnetic Interference (EMI)
I Operates at 3.3 V power supply
I Operating temperature range from 40 °C to +85 °C
I Available in 64-pin LQFP and TFBGA packages
3.
Applications
The ISP1362 can be used to implement a dual-role USB device in any application, USB
host or USB peripheral, depending on the cable connection. If the dual-role device is
connected to a typical USB peripheral, it behaves like a typical USB host. The dual-role
device, however, can also be connected to a PC or any other USB host and behave like a
typical USB peripheral.
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