參數(shù)資料
型號(hào)： ISP1362EE,551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù)： 149/152頁
文件大?。?/td> 677K
代理商： ISP1362EE,551
ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
96 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
14.6.2 HcDirectAddressLength register (R/W: 32h/B2h)
The HcDirectAddressLength register is used for direct addressing of the ISTL, INTL or
ATL buffers. This register species the starting address of the buffer and byte count of
data to be addressed. Therefore, it allows the programmer to randomly access the buffer.
The bit allocation of the register is given in Table 78.
Code (Hex): 32 — read
Code (Hex): B2 — write
8
ISTL0BufferDone
0 — The ISTL0 buffer has not yet been read by the Host
Controller.
1 — The ISTL0 buffer has been read by the Host Controller.
7
-
reserved
6
ISTL1_ActiveStatus
0 — The ISTL1 buffer is not accessed by the slave host.
1 — The ISTL1 buffer is accessed by the slave host.
5
ISTL0_ActiveStatus
0 — The ISTL0 buffer is not accessed by the slave host.
1 — The ISTL0 buffer is accessed by the slave host.
4
Reset_HWPingPong
Reg
0to1 — Resets the internal hardware ping pong register to 0
when ATL_Active is 0. The hardware ping pong register can be
read from bit 10 of this register.
1to0 — Has no effect.
3
ATL_Active
0 — The Host Controller does not process the ATL buffer.
1 — The Host Controller processes the ATL buffer.
2
INTL_Active
0 — The Host Controller does not process the INTL buffer.
1 — The Host Controller processes the INTL buffer.
1
ISTL1BufferFull
0 — The Host Controller does not process the ISTL1 buffer.
1 — The Host Controller processes the ISTL1 buffer.
0
ISTL0BufferFull
0 — The Host Controller does not process the ISTL0 buffer.
1 — The Host Controller processes the ISTL0 buffer.
Table 77.
HcBufferStatus register: bit description …continued
Bit
Symbol
Description
Table 78.
HcDirectAddressLength register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
DataByteCount[15:8]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
DataByteCount[7:0]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
BufferStartAddress[14:8]
Reset
00000000
Access
-
R/W
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