參數(shù)資料
型號： ISP1362EE,551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù)： 144/152頁
文件大?。?/td> 677K
代理商： ISP1362EE,551
ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
91 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
14.4.3 HcTransferCounter register (R/W: 22h/A2h)
Regardless of PIO or DMA data transfer modes, this register is used to initialize the
number of bytes to be transferred to or from the ISTL, INTL or ATL buffer RAM. For the
count value loaded in the register to take effect, the HCD is required to set bit 7 of the
HcDMAConguration register to logic 1. When the count value has reached, the Host
Controller must generate an internal EOT signal to set bit 2 of the Hc
PInterrupt register,
AllEOTInterrupt, and update the HcBufferStatus register. The bit allocation of the
HcTransferCounter register is given in Table 68.
Code (Hex): 22 — read
Code (Hex): A2 — write
14.4.4 Hc
PInterrupt register (R/W: 24h/A4h)
All the bits in this register are active at power-on reset. None of the active bits, however,
will cause an interrupt on the interrupt pin (INT1), unless they are set by the respective
bits in the Hc
PInterruptEnable register and bit 0 of the HcHardwareConguration register
is also set.
The bits in this register are cleared only when you write to this register, indicating the bits
to be cleared. To clear all the enabled bits in this register, the HCD must write FFh to this
register.
The bit allocation of the Hc
PInterrupt register is given in Table 69.
Code (Hex): 24 — read
Code (Hex): A4 — write
4
DMAEnable
0 — DMA is disabled
1 — DMA is enabled
This bit needs to be reset when the DMA transfer is completed.
3 to 1
Buffer_Type_Select[2:0] See Table 67.
0
DMAReadWriteSelect
0 — read from the buffer memory of the Host Controller
1 — write to the buffer memory of the Host Controller
Table 67.
Buffer_Type_Select[2:0]: bit description
Bit 3
Bit 2
Bit 1
Buffer Type
0
ISTL0 (default)
0
1
ISTL1
0
1
0
INTL
011ATL
1
X
direct addressing
Table 66.
HcDMAConguration register: bit description …continued
Bit
Symbol
Description
Table 68.
HcTransferCounter register: bit description
Bit
Symbol
Access
Value
Description
15 to 0
CounterValue[15:0]
R/W
0000h
Number of data bytes to be read from or written to the buffer RAM.
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