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| 型號(hào)： | ISP1362EE,551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封裝： | 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64 |
| 文件頁(yè)數(shù)： | 100/152頁(yè) |
| 文件大?。?/td> | 677K |
| 代理商： | ISP1362EE,551 |
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ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
51 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
12.2 Device DMA transfer
12.2.1 DMA for an IN endpoint (internal Peripheral Controller to the external USB
host)
When the internal DMA handler is enabled and at least one buffer (ping or pong) is free,
the DREQ2 line is asserted. The external DMA controller then starts negotiating for
control of the bus. As soon as it has access, it asserts the DACK2 line and starts writing
data. The burst length is programmable. When the number of bytes equal to the burst
length has been written, the DREQ2 line is de-asserted. As a result, the DMA controller
de-asserts the DACK2 line and releases the bus. At that moment, the whole cycle restarts
for the next burst.
When the buffer is full, the DREQ2 line is de-asserted and the buffer is validated (which
means that it is sent to the host at the next IN token). When the DMA transfer is
terminated, the buffer is also validated (even if it is not full). A DMA transfer is terminated
when any of the following conditions is met:
The DMA count is complete.
DMAEN = 0.
Remark: If the OneDMA bit in the HcHardwareConguration register is set to logic 1,
Peripheral Controller DMA controller handshake signals DREQ2 and DACK2 are routed to
DREQ1 and DACK1.
12.2.2 DMA for OUT endpoint (external USB host to internal Peripheral Controller)
When the internal DMA handler is enabled and at least one buffer is full, the DREQ2 line
is asserted. The external DMA controller then starts negotiating for control of the bus, and
as soon as it has access, it asserts the DACK2 line and starts reading data. The burst
length is programmable. When the number of bytes equal to the burst length has been
read, the DREQ2 line is de-asserted. As a result, the DMA controller de-asserts the
DACK2 line and releases the bus. At that moment, the whole cycle restarts for the next
burst. When all the data is read, the DREQ2 line is de-asserted and the buffer is cleared
(this means that it can be overwritten when a new packet arrives). A DMA transfer is
terminated when any of the following conditions are met:
The DMA count is complete.
DMAEN = 0.
Remark: If the OneDMA bit in the HcHardwareConguration register is set to logic 1,
Peripheral Controller DMA controller handshake signals DREQ2 and DACK2 are routed to
DREQ1 and DACK1.
When the DMA transfer is terminated, the buffer is also cleared (even if data is not
completely read) and the DMA handler is automatically disabled. For the next DMA
transfer, the DMA controller as well as the DMA handler must be re-enabled.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1362EE-S | 功能描述:IC USB CTRL SNGL CHIP 64TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1362EE-T | 功能描述:USB 接口集成電路 USB OTG HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1362EEUM | 功能描述:IC USB OTG CONTROLLER 64-TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1362PCI/DOSOTG | 制造商:NXP Semiconductors 功能描述: |
| ISP1501 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Hi-Speed Universal Serial Bus peripheral transceiver |
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