參數(shù)資料
型號： ISP1362EE,551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù)： 114/152頁
文件大?。?/td> 677K
代理商： ISP1362EE,551
ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
64 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
Table 27.
OtgInterrupt register: bit description
Bit
Symbol
Description
15 to 11
-
reserved
10
OTG_TMR_
TIMEOUT
This bit is set whenever the OTG timer attains time-out. Writing logic 1
clears this bit. Writing logic 0 has no effect.
0 — no event
1 — OTG timer time-out
9
B_SE0_SRP This bit is set whenever the device detects more than 2 ms of SE0.
Writing logic 1 clears this bit. Writing logic 0 has no effect.
0 — no event
1 — bus has been in SE0 for more than 2 ms
8
A_SRP_DET This bit is used to detect the Session Request Event (SRP) from the
remote device. The SRP event can be either VBUS pulsing or data line
pulsing. Bit 9 (A_SEL_SRP) of the OtgControl register determines
which SRP is selected. Writing logic 1 clears this bit. Writing logic 0
has no effect.
0 — no event
1 — SRP is detected
7
OTG_
RESUME
This bit is used to detect a J to K state change when the device is in
the ‘suspend’ state. Writing logic 1 clears this bit. Writing logic 0 has
no effect.
0 — no event
1 — a resume signal (J
→ K) is detected when the bus is in the
‘suspend’ state
6
OTG_
SUSPND
This bit is set whenever the OTG port goes into the suspend state (bus
idle for > 3 ms). Write logic 1 to clear this bit. Writing logic 0 has no
effect.
0 — no event
1 — suspend (bus idle for > 3 ms)
5
RMT_
CONN_C
This bit is set whenever the RMT_CONN bit of the OtgStatus register
changes. Write logic 1 to clear this bit. Writing logic 0 has no effect.
0 — no event
1 — RMT_CONN bit has changed
4
B_SESS_
VLD_C
This bit is set whenever the B_SESS_VLD bit of the OtgStatus register
changes. Write logic 1 to clear this bit. Writing logic 0 has no effect.
0 — no event
1 — bit B_SESS_VLD has changed
3
A_SESS_
VLD_C
This bit is set whenever the A_SESS_VLD bit of the OtgStatus register
changes. Write logic 1 to clear this bit. Writing logic 0 has no effect.
0 — no event
1 — bit A_SESS_VLD has changed
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