參數(shù)資料
型號(hào)： ISP1362EE,551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù)： 3/152頁
文件大?。?/td> 677K
代理商： ISP1362EE,551
ISP1362_5
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 8 May 2007
100 of 152
NXP Semiconductors
ISP1362
Single-chip USB OTG Controller
14.8.3 HcINTLBlkSize register (R/W: 53h/D3h)
The ISP1362 requires the INTL buffer to be partitioned into several equal sized blocks so
that the Host Controller can skip the current PTD and proceed to process the next PTD
easily. The block size of the INTL buffer is required to be specied in this register and must
be a multiple of 8 bytes. The default value of the block size is 64 bytes, and the maximum
allowable block size is 1024 bytes. Table 88 shows the bit allocation of the register.
Code (Hex): 53 — read
Code (Hex): D3 — write
14.8.4 HcINTLPTDDoneMap register (R: 17h)
This is a 32-bit register, and the bit description is given in Table 90. Every bit of the
register represents the processing status of a PTD. Bit 0 of the register represents the rst
PTD stored in the INTL buffer, bit 1 represents the second PTD stored in the buffer, and so
on. The register is updated once every ms by the Host Controller and is cleared on read
by the HCD. Bits that are set represent its corresponding PTDs are processed by the Host
Controller and the ACK token is received from the device.
Code (Hex): 17 — read only
14.8.5 HcINTLPTDSkipMap register (R/W: 18h/98h)
This is a 32-bit register, and the bit description is given in Table 91. Bit 0 of the register
represents the rst PTD stored in the INTL buffer, bit 1 represents the second PTD stored
in the buffer, and so on. When a bit is set by the HCD, the corresponding PTD is skipped
and is not processed by the Host Controller. The Host Controller processes the skipped
Table 88.
HcINTLBlkSize register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
BlockSize[9:8]
Reset
------
0
Access
------
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
BlockSize[7:0]
Reset
00000000
Access
R/W
Table 89.
HcINTLBlkSize register: bit description
Bit
Symbol
Description
15 to 10
-
reserved
9 to 0
BlockSize[9:0]
The block size of the INTL buffer.
Table 90.
HcINTLPTDDoneMap register: bit description
Bit
Symbol
Access
Value
Description
31 to 0
PTDDoneBits[31:0] R
0000h
0 — The PTD stored in the INTL buffer has not successfully been
processed by the Host Controller.
1 — The PTD stored in the INTL buffer has successfully been
processed by the Host Controller.
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